From 44484ac0263c641cde596ee80f4e491ae26ccaa4 Mon Sep 17 00:00:00 2001 From: Robert Peip Date: Wed, 26 Oct 2022 09:12:57 +0200 Subject: [PATCH] corrected information about running CPU and DMA in parallel --- docs/dmachannels.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/dmachannels.md b/docs/dmachannels.md index f005769..38bceb8 100644 --- a/docs/dmachannels.md +++ b/docs/dmachannels.md @@ -196,10 +196,10 @@ cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle plus 6 waitstates, ie. 7 cycles in total)
#### CPU Operation during DMA -Basically, the CPU is stopped during DMA (theoretically, the CPU could be kept -running when accessing only cache, scratchpad and on-chip I/O ports like DMA -registers, and during the CDROM/SPU/PIO waitstates it could even access Main -RAM, but these situations aren't supported).
-However, the CPU operation resumes during periods when DMA gets interrupted +CPU is running during DMA within very strict rules. It can be kept running when accessing only cache, scratchpad, COP0 and GTE.
+It can also make use of the 4 entry Write queue for both RAM and I/O registers, see:
+[Write queue](memorymap.md#Write-queue)
+Any read access from RAM or I/O registers or filling more than 4 entries into the write queue will stall the CPU until the DMA is finished.
+Additionally, the CPU operation resumes during periods when DMA gets interrupted (ie. after SyncMode 1 blocks, after SyncMode 2 list entries) (or in SyncMode 0 with Chopping enabled).