1100 lines
34 KiB
C++
1100 lines
34 KiB
C++
// cpu.cpp - originally written and placed in the public domain by Wei Dai
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#include "pch.h"
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#include "config.h"
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#ifndef EXCEPTION_EXECUTE_HANDLER
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# define EXCEPTION_EXECUTE_HANDLER 1
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#endif
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#ifndef CRYPTOPP_IMPORTS
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#include "cpu.h"
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#include "misc.h"
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#include "stdcpp.h"
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#ifdef _AIX
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# include <sys/systemcfg.h>
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#endif
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#ifdef __linux__
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# include <unistd.h>
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#endif
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// Capability queries, requires Glibc 2.16, http://lwn.net/Articles/519085/
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// CRYPTOPP_GLIBC_VERSION not used because config.h is missing <feature.h>
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#if (((__GLIBC__ * 100) + __GLIBC_MINOR__) >= 216)
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# define CRYPTOPP_GETAUXV_AVAILABLE 1
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#endif
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#if CRYPTOPP_GETAUXV_AVAILABLE
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# include <sys/auxv.h>
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#else
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#ifndef AT_HWCAP
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# define AT_HWCAP 16
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#endif
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#ifndef AT_HWCAP2
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# define AT_HWCAP2 26
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#endif
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unsigned long int getauxval(unsigned long int) { return 0; }
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#endif
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#if defined(__APPLE__)
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# include <sys/utsname.h>
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#endif
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// The cpu-features header and source file are located in
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// "$ANDROID_NDK_ROOT/sources/android/cpufeatures".
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// setenv-android.sh will copy the header and source file
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// into PWD and the makefile will build it in place.
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#if defined(__ANDROID__)
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# include "cpu-features.h"
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#endif
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#ifdef CRYPTOPP_GNU_STYLE_INLINE_ASSEMBLY
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# include <signal.h>
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# include <setjmp.h>
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#endif
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// Visual Studio 2008 and below is missing _xgetbv. See x64dll.asm for the body.
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#if defined(_MSC_VER) && _MSC_VER <= 1500 && defined(_M_X64)
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extern "C" unsigned long long __fastcall ExtendedControlRegister(unsigned int);
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#endif
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ANONYMOUS_NAMESPACE_BEGIN
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#if defined(__APPLE__)
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enum {PowerMac=1, Mac, iPhone, iPod, iPad, AppleTV, AppleWatch};
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void GetAppleMachineInfo(unsigned int& device, unsigned int& version)
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{
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device = version = 0;
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struct utsname systemInfo;
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systemInfo.machine[0] = '\0';
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uname(&systemInfo);
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std::string machine(systemInfo.machine);
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if (machine.find("PowerMac") != std::string::npos ||
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machine.find("Power Macintosh") != std::string::npos)
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device = PowerMac;
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else if (machine.find("Mac") != std::string::npos ||
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machine.find("Macintosh") != std::string::npos)
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device = Mac;
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else if (machine.find("iPhone") != std::string::npos)
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device = iPhone;
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else if (machine.find("iPod") != std::string::npos)
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device = iPod;
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else if (machine.find("iPad") != std::string::npos)
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device = iPad;
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else if (machine.find("AppleTV") != std::string::npos)
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device = AppleTV;
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else if (machine.find("AppleWatch") != std::string::npos)
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device = AppleWatch;
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std::string::size_type pos = machine.find_first_of("0123456789");
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if (pos != std::string::npos)
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version = std::atoi(machine.substr(pos).c_str());
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}
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// http://stackoverflow.com/questions/45637888/how-to-determine-armv8-features-at-runtime-on-ios
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bool IsAppleMachineARMv8(unsigned int device, unsigned int version)
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{
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if ((device == iPhone && version >= 6) ||
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(device == iPad && version >= 4))
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{
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return true;
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}
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return false;
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}
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bool IsAppleMachineARMv84(unsigned int device, unsigned int version)
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{
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return false;
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}
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#endif // __APPLE__
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ANONYMOUS_NAMESPACE_END
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NAMESPACE_BEGIN(CryptoPP)
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#ifndef CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
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extern "C" {
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typedef void (*SigHandler)(int);
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}
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extern "C"
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{
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static jmp_buf s_jmpNoCPUID;
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static void SigIllHandlerCPUID(int unused)
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{
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CRYPTOPP_UNUSED(unused);
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longjmp(s_jmpNoCPUID, 1);
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}
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}
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#endif // Not CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY
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// *************************** IA-32 CPUs ***************************
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#if (CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64)
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extern bool CPU_ProbeSSE2();
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#if _MSC_VER >= 1600
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inline bool CpuId(word32 func, word32 subfunc, word32 output[4])
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{
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__cpuidex((int *)output, func, subfunc);
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return true;
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}
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#elif _MSC_VER >= 1400 && CRYPTOPP_BOOL_X64
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inline bool CpuId(word32 func, word32 subfunc, word32 output[4])
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{
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if (subfunc != 0)
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return false;
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__cpuid((int *)output, func);
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return true;
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}
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#else
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// Borland/Embarcadero and Issue 498
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// cpu.cpp (131): E2211 Inline assembly not allowed in inline and template functions
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bool CpuId(word32 func, word32 subfunc, word32 output[4])
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{
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#if defined(CRYPTOPP_MS_STYLE_INLINE_ASSEMBLY) || defined(__BORLANDC__)
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__try
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{
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// Borland/Embarcadero and Issue 500
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// Local variables for cpuid output
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word32 a, b, c, d;
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__asm
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{
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mov eax, func
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mov ecx, subfunc
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cpuid
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mov [a], eax
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mov [b], ebx
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mov [c], ecx
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mov [d], edx
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}
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output[0] = a;
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output[1] = b;
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output[2] = c;
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output[3] = d;
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}
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// GetExceptionCode() == EXCEPTION_ILLEGAL_INSTRUCTION
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__except (EXCEPTION_EXECUTE_HANDLER)
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{
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return false;
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}
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// func = 0 returns the highest basic function understood in EAX. If the CPU does
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// not return non-0, then it is mostly useless. The code below converts basic
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// function value to a true/false return value.
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if(func == 0)
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return output[0] != 0;
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return true;
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#else
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// longjmp and clobber warnings. Volatile is required.
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// http://github.com/weidai11/cryptopp/issues/24 and http://stackoverflow.com/q/7721854
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volatile bool result = true;
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volatile SigHandler oldHandler = signal(SIGILL, SigIllHandlerCPUID);
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if (oldHandler == SIG_ERR)
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return false;
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# ifndef __MINGW32__
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volatile sigset_t oldMask;
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if (sigprocmask(0, NULLPTR, (sigset_t*)&oldMask) != 0)
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return false;
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# endif
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if (setjmp(s_jmpNoCPUID))
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result = false;
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else
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{
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asm volatile
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(
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// save ebx in case -fPIC is being used
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// TODO: this might need an early clobber on EDI.
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# if CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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"pushq %%rbx; cpuid; mov %%ebx, %%edi; popq %%rbx"
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# else
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"push %%ebx; cpuid; mov %%ebx, %%edi; pop %%ebx"
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# endif
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: "=a" (output[0]), "=D" (output[1]), "=c" (output[2]), "=d" (output[3])
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: "a" (func), "c" (subfunc)
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: "cc"
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);
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}
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# ifndef __MINGW32__
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sigprocmask(SIG_SETMASK, (sigset_t*)&oldMask, NULLPTR);
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# endif
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signal(SIGILL, oldHandler);
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return result;
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#endif
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}
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#endif
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bool CRYPTOPP_SECTION_INIT g_x86DetectionDone = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSSE3 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE41 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE42 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAVX = false;
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bool CRYPTOPP_SECTION_INIT g_hasAVX2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAESNI = false;
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bool CRYPTOPP_SECTION_INIT g_hasCLMUL = false;
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bool CRYPTOPP_SECTION_INIT g_hasADX = false;
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bool CRYPTOPP_SECTION_INIT g_hasSHA = false;
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bool CRYPTOPP_SECTION_INIT g_hasRDRAND = false;
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bool CRYPTOPP_SECTION_INIT g_hasRDSEED = false;
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bool CRYPTOPP_SECTION_INIT g_isP4 = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockRNG = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockACE = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockACE2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockPHE = false;
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bool CRYPTOPP_SECTION_INIT g_hasPadlockPMM = false;
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word32 CRYPTOPP_SECTION_INIT g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
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static inline bool IsIntel(const word32 output[4])
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{
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// This is the "GenuineIntel" string
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return (output[1] /*EBX*/ == 0x756e6547) &&
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(output[2] /*ECX*/ == 0x6c65746e) &&
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(output[3] /*EDX*/ == 0x49656e69);
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}
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static inline bool IsAMD(const word32 output[4])
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{
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// This is the "AuthenticAMD" string. Some early K5's can return "AMDisbetter!"
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return (output[1] /*EBX*/ == 0x68747541) &&
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(output[2] /*ECX*/ == 0x444D4163) &&
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(output[3] /*EDX*/ == 0x69746E65);
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}
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static inline bool IsHygon(const word32 output[4])
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{
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// This is the "HygonGenuine" string.
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return (output[1] /*EBX*/ == 0x6f677948) &&
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(output[2] /*ECX*/ == 0x656e6975) &&
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(output[3] /*EDX*/ == 0x6e65476e);
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}
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static inline bool IsVIA(const word32 output[4])
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{
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// This is the "CentaurHauls" string. Some non-PadLock's can return "VIA VIA VIA "
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return (output[1] /*EBX*/ == 0x746e6543) &&
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(output[2] /*ECX*/ == 0x736c7561) &&
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(output[3] /*EDX*/ == 0x48727561);
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}
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void DetectX86Features()
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{
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// Coverity finding CID 171239...
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word32 cpuid0[4]={0}, cpuid1[4]={0}, cpuid2[4]={0};
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if (!CpuId(0, 0, cpuid0))
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return;
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if (!CpuId(1, 0, cpuid1))
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return;
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// cpuid1[2] & (1 << 27) is XSAVE/XRESTORE and signals OS support for SSE; use it to avoid probes.
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// See http://github.com/weidai11/cryptopp/issues/511 and http://stackoverflow.com/a/22521619/608639
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if ((cpuid1[3] & (1 << 26)) != 0)
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g_hasSSE2 = ((cpuid1[2] & (1 << 27)) != 0) || CPU_ProbeSSE2();
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g_hasSSSE3 = g_hasSSE2 && ((cpuid1[2] & (1<< 9)) != 0);
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g_hasSSE41 = g_hasSSE2 && ((cpuid1[2] & (1<<19)) != 0);
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g_hasSSE42 = g_hasSSE2 && ((cpuid1[2] & (1<<20)) != 0);
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g_hasAESNI = g_hasSSE2 && ((cpuid1[2] & (1<<25)) != 0);
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g_hasCLMUL = g_hasSSE2 && ((cpuid1[2] & (1<< 1)) != 0);
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// AVX is similar to SSE, but check both bits 27 (SSE) and 28 (AVX).
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// https://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
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CRYPTOPP_CONSTANT(YMM_FLAG = (3 << 1))
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CRYPTOPP_CONSTANT(AVX_FLAG = (3 << 27))
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if ((cpuid1[2] & AVX_FLAG) == AVX_FLAG)
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{
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// Unable to perform the necessary tests
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#if defined(CRYPTOPP_DISABLE_ASM)
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g_hasAVX = false;
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// GCC 4.1/Binutils 2.17 cannot consume xgetbv
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#elif defined(__GNUC__) || (__SUNPRO_CC >= 0x5100) || defined(__BORLANDC__)
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// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71659 and
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// http://www.agner.org/optimize/vectorclass/read.php?i=65
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word32 a=0, d=0;
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__asm __volatile
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(
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// "xgetbv" : "=a"(a), "=d"(d) : "c"(0) :
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".byte 0x0f, 0x01, 0xd0" "\n\t"
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: "=a"(a), "=d"(d) : "c"(0) : "cc"
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);
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word64 xcr0 = a | static_cast<word64>(d) << 32;
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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// Visual Studio 2008 and below lack xgetbv
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#elif defined(_MSC_VER) && _MSC_VER <= 1500 && defined(_M_IX86)
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word32 a=0, d=0;
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__asm {
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push eax
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push edx
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push ecx
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mov ecx, 0
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_emit 0x0f
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_emit 0x01
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_emit 0xd0
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mov a, eax
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mov d, edx
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pop ecx
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pop edx
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pop eax
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}
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word64 xcr0 = a | static_cast<word64>(d) << 32;
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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// Visual Studio 2008 and below lack xgetbv
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#elif defined(_MSC_VER) && _MSC_VER <= 1500 && defined(_M_X64)
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word64 xcr0 = ExtendedControlRegister(0);
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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// Downlevel SunCC
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#elif defined(__SUNPRO_CC)
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g_hasAVX = false;
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// _xgetbv is available
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#else
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word64 xcr0 = _xgetbv(0);
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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#endif
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}
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if (IsIntel(cpuid0))
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{
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CRYPTOPP_CONSTANT(RDRAND_FLAG = (1 << 30))
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CRYPTOPP_CONSTANT(RDSEED_FLAG = (1 << 18))
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CRYPTOPP_CONSTANT( ADX_FLAG = (1 << 19))
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CRYPTOPP_CONSTANT( SHA_FLAG = (1 << 29))
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CRYPTOPP_CONSTANT( AVX2_FLAG = (1 << 5))
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g_isP4 = ((cpuid1[0] >> 8) & 0xf) == 0xf;
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g_cacheLineSize = 8 * GETBYTE(cpuid1[1], 1);
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g_hasRDRAND = (cpuid1[2] /*ECX*/ & RDRAND_FLAG) != 0;
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if (cpuid0[0] /*EAX*/ >= 7)
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{
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if (CpuId(7, 0, cpuid2))
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{
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g_hasRDSEED = (cpuid2[1] /*EBX*/ & RDSEED_FLAG) != 0;
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g_hasADX = (cpuid2[1] /*EBX*/ & ADX_FLAG) != 0;
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g_hasSHA = (cpuid2[1] /*EBX*/ & SHA_FLAG) != 0;
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g_hasAVX2 = (cpuid2[1] /*EBX*/ & AVX2_FLAG) != 0;
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}
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}
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}
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else if (IsAMD(cpuid0) || IsHygon(cpuid0))
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{
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CRYPTOPP_CONSTANT(RDRAND_FLAG = (1 << 30))
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CRYPTOPP_CONSTANT(RDSEED_FLAG = (1 << 18))
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CRYPTOPP_CONSTANT( ADX_FLAG = (1 << 19))
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CRYPTOPP_CONSTANT( SHA_FLAG = (1 << 29))
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CRYPTOPP_CONSTANT( AVX2_FLAG = (1 << 5))
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CpuId(0x80000005, 0, cpuid2);
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g_cacheLineSize = GETBYTE(cpuid2[2], 0);
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g_hasRDRAND = (cpuid1[2] /*ECX*/ & RDRAND_FLAG) != 0;
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if (cpuid0[0] /*EAX*/ >= 7)
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{
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if (CpuId(7, 0, cpuid2))
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{
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g_hasRDSEED = (cpuid2[1] /*EBX*/ & RDSEED_FLAG) != 0;
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g_hasADX = (cpuid2[1] /*EBX*/ & ADX_FLAG) != 0;
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g_hasSHA = (cpuid2[1] /*EBX*/ & SHA_FLAG) != 0;
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g_hasAVX2 = (cpuid2[1] /*EBX*/ & AVX2_FLAG) != 0;
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}
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}
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}
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else if (IsVIA(cpuid0))
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{
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CRYPTOPP_CONSTANT( RNG_FLAGS = (0x3 << 2))
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CRYPTOPP_CONSTANT( ACE_FLAGS = (0x3 << 6))
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CRYPTOPP_CONSTANT(ACE2_FLAGS = (0x3 << 8))
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CRYPTOPP_CONSTANT( PHE_FLAGS = (0x3 << 10))
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CRYPTOPP_CONSTANT( PMM_FLAGS = (0x3 << 12))
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CpuId(0xC0000000, 0, cpuid2);
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if (cpuid2[0] >= 0xC0000001)
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{
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// Extended features available
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CpuId(0xC0000001, 0, cpuid2);
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g_hasPadlockRNG = (cpuid2[3] /*EDX*/ & RNG_FLAGS) == RNG_FLAGS;
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g_hasPadlockACE = (cpuid2[3] /*EDX*/ & ACE_FLAGS) == ACE_FLAGS;
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g_hasPadlockACE2 = (cpuid2[3] /*EDX*/ & ACE2_FLAGS) == ACE2_FLAGS;
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g_hasPadlockPHE = (cpuid2[3] /*EDX*/ & PHE_FLAGS) == PHE_FLAGS;
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g_hasPadlockPMM = (cpuid2[3] /*EDX*/ & PMM_FLAGS) == PMM_FLAGS;
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}
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}
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if (g_cacheLineSize == 0)
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g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
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*const_cast<volatile bool*>(&g_x86DetectionDone) = true;
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}
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// *************************** ARM-32, Aarch32 and Aarch64 ***************************
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#elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8)
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bool CRYPTOPP_SECTION_INIT g_ArmDetectionDone = false;
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bool CRYPTOPP_SECTION_INIT g_hasARMv7 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasNEON = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasPMULL = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasCRC32 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasAES = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA1 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA2 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA512 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA3 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSM3 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSM4 = false;
|
|
word32 CRYPTOPP_SECTION_INIT g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
|
|
|
|
// ARM does not have an unprivliged equivalent to CPUID on IA-32. We have to jump through some
|
|
// hoops to detect features on a wide array of platforms. Our strategy is two part. First,
|
|
// attempt to *Query* the OS for a feature, like using getauxval on Linux. If that fails,
|
|
// then *Probe* the cpu executing an instruction and an observe a SIGILL if unsupported.
|
|
// The probes are in source files where compilation options like -march=armv8-a+crc make
|
|
// intrinsics available. They are expensive when compared to a standard OS feature query.
|
|
// Always perform the feature quesry first. For Linux see
|
|
// http://sourceware.org/ml/libc-help/2017-08/msg00012.html
|
|
// Avoid probes on Apple platforms because Apple's signal handling for SIGILLs appears broken.
|
|
// We are trying to figure out a way to feature test without probes. Also see
|
|
// http://stackoverflow.com/a/11197770/608639 and
|
|
// http://gist.github.com/erkanyildiz/390a480f27e86f8cd6ba
|
|
|
|
extern bool CPU_ProbeARMv7();
|
|
extern bool CPU_ProbeNEON();
|
|
extern bool CPU_ProbeCRC32();
|
|
extern bool CPU_ProbeAES();
|
|
extern bool CPU_ProbeSHA1();
|
|
extern bool CPU_ProbeSHA2();
|
|
extern bool CPU_ProbeSHA512();
|
|
extern bool CPU_ProbeSHA3();
|
|
extern bool CPU_ProbeSM3();
|
|
extern bool CPU_ProbeSM4();
|
|
extern bool CPU_ProbePMULL();
|
|
|
|
// https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/hwcap.h
|
|
#ifndef HWCAP_ARMv7
|
|
# define HWCAP_ARMv7 (1 << 29)
|
|
#endif
|
|
#ifndef HWCAP_ASIMD
|
|
# define HWCAP_ASIMD (1 << 1)
|
|
#endif
|
|
#ifndef HWCAP_ARM_NEON
|
|
# define HWCAP_ARM_NEON 4096
|
|
#endif
|
|
#ifndef HWCAP_CRC32
|
|
# define HWCAP_CRC32 (1 << 7)
|
|
#endif
|
|
#ifndef HWCAP2_CRC32
|
|
# define HWCAP2_CRC32 (1 << 4)
|
|
#endif
|
|
#ifndef HWCAP_PMULL
|
|
# define HWCAP_PMULL (1 << 4)
|
|
#endif
|
|
#ifndef HWCAP2_PMULL
|
|
# define HWCAP2_PMULL (1 << 1)
|
|
#endif
|
|
#ifndef HWCAP_AES
|
|
# define HWCAP_AES (1 << 3)
|
|
#endif
|
|
#ifndef HWCAP2_AES
|
|
# define HWCAP2_AES (1 << 0)
|
|
#endif
|
|
#ifndef HWCAP_SHA1
|
|
# define HWCAP_SHA1 (1 << 5)
|
|
#endif
|
|
#ifndef HWCAP_SHA2
|
|
# define HWCAP_SHA2 (1 << 6)
|
|
#endif
|
|
#ifndef HWCAP2_SHA1
|
|
# define HWCAP2_SHA1 (1 << 2)
|
|
#endif
|
|
#ifndef HWCAP2_SHA2
|
|
# define HWCAP2_SHA2 (1 << 3)
|
|
#endif
|
|
#ifndef HWCAP_SHA3
|
|
# define HWCAP_SHA3 (1 << 17)
|
|
#endif
|
|
#ifndef HWCAP_SM3
|
|
# define HWCAP_SM3 (1 << 18)
|
|
#endif
|
|
#ifndef HWCAP_SM4
|
|
# define HWCAP_SM4 (1 << 19)
|
|
#endif
|
|
#ifndef HWCAP_SHA512
|
|
# define HWCAP_SHA512 (1 << 21)
|
|
#endif
|
|
|
|
inline bool CPU_QueryARMv7()
|
|
{
|
|
#if defined(__aarch32__) || defined(__aarch64__)
|
|
// ARMv7 or above
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__arm__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_ARMv7) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__arm__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_ARMv7) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__arm__)
|
|
// Apple hardware is ARMv7 or above.
|
|
return true;
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QueryNEON()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_ASIMD) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__arm__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_NEON) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_ASIMD) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_ASIMD) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__arm__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_ARM_NEON) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
// Core feature set for Aarch32 and Aarch64.
|
|
return true;
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QueryCRC32()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_CRC32) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_CRC32) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_CRC32) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_CRC32) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
// No compiler support. CRC intrinsics result in a failed compiled.
|
|
return false;
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QueryPMULL()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_PMULL) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_PMULL) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_PMULL) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_PMULL) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
// No compiler support. PMULL intrinsics result in a failed compiled.
|
|
return false;
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QueryAES()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_AES) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_AES) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_AES) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_AES) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv8(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySHA1()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SHA1) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SHA1) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SHA1) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SHA1) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv8(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySHA2()
|
|
{
|
|
#if defined(__ANDROID__) && defined(__aarch64__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SHA2) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__)
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SHA2) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SHA2) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SHA2) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__)
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv8(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySHA512()
|
|
{
|
|
// Some ARMv8.4 features are disabled at the moment
|
|
#if defined(__ANDROID__) && defined(__aarch64__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SHA512) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SHA512) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SHA512) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SHA512) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__) && 0
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv84(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySHA3()
|
|
{
|
|
// Some ARMv8.4 features are disabled at the moment
|
|
#if defined(__ANDROID__) && defined(__aarch64__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SHA3) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SHA3) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SHA3) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SHA3) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__) && 0
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv84(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySM3()
|
|
{
|
|
// Some ARMv8.4 features are disabled at the moment
|
|
#if defined(__ANDROID__) && defined(__aarch64__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SM3) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SM3) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SM3) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SM3) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__) && 0
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv84(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
inline bool CPU_QuerySM4()
|
|
{
|
|
// Some ARMv8.4 features are disabled at the moment
|
|
#if defined(__ANDROID__) && defined(__aarch64__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM64) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM64_FEATURE_SM4) != 0))
|
|
return true;
|
|
#elif defined(__ANDROID__) && defined(__aarch32__) && 0
|
|
if (((android_getCpuFamily() & ANDROID_CPU_FAMILY_ARM) != 0) &&
|
|
((android_getCpuFeatures() & ANDROID_CPU_ARM_FEATURE_SM4) != 0))
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch64__)
|
|
if ((getauxval(AT_HWCAP) & HWCAP_SM4) != 0)
|
|
return true;
|
|
#elif defined(__linux__) && defined(__aarch32__)
|
|
if ((getauxval(AT_HWCAP2) & HWCAP2_SM4) != 0)
|
|
return true;
|
|
#elif defined(__APPLE__) && defined(__aarch64__) && 0
|
|
unsigned int device, version;
|
|
GetAppleMachineInfo(device, version);
|
|
return IsAppleMachineARMv84(device, version);
|
|
#endif
|
|
return false;
|
|
}
|
|
|
|
void DetectArmFeatures()
|
|
{
|
|
// The CPU_ProbeXXX's return false for OSes which
|
|
// can't tolerate SIGILL-based probes
|
|
g_hasARMv7 = CPU_QueryARMv7() || CPU_ProbeARMv7();
|
|
g_hasNEON = CPU_QueryNEON() || CPU_ProbeNEON();
|
|
g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();
|
|
g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();
|
|
g_hasAES = CPU_QueryAES() || CPU_ProbeAES();
|
|
g_hasSHA1 = CPU_QuerySHA1() || CPU_ProbeSHA1();
|
|
g_hasSHA2 = CPU_QuerySHA2() || CPU_ProbeSHA2();
|
|
g_hasSHA512 = CPU_QuerySHA512(); // || CPU_ProbeSHA512();
|
|
g_hasSHA3 = CPU_QuerySHA3(); // || CPU_ProbeSHA3();
|
|
g_hasSM3 = CPU_QuerySM3(); // || CPU_ProbeSM3();
|
|
g_hasSM4 = CPU_QuerySM4(); // || CPU_ProbeSM4();
|
|
|
|
#if defined(__linux__) && defined(_SC_LEVEL1_DCACHE_LINESIZE)
|
|
// Glibc does not implement on some platforms. The runtime returns 0 instead of error.
|
|
// https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c
|
|
int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
|
|
if (cacheLineSize > 0)
|
|
g_cacheLineSize = cacheLineSize;
|
|
#endif
|
|
|
|
*const_cast<volatile bool*>(&g_ArmDetectionDone) = true;
|
|
}
|
|
|
|
// *************************** PowerPC and PowerPC64 ***************************
|
|
|
|
#elif (CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)
|
|
|
|
bool CRYPTOPP_SECTION_INIT g_PowerpcDetectionDone = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasAltivec = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasPower7 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasPower8 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasPower9 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasAES = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasPMULL = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA256 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasSHA512 = false;
|
|
bool CRYPTOPP_SECTION_INIT g_hasDARN = false;
|
|
word32 CRYPTOPP_SECTION_INIT g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
|
|
|
|
extern bool CPU_ProbeAltivec();
|
|
extern bool CPU_ProbePower7();
|
|
extern bool CPU_ProbePower8();
|
|
extern bool CPU_ProbePower9();
|
|
extern bool CPU_ProbeAES();
|
|
extern bool CPU_ProbePMULL();
|
|
extern bool CPU_ProbeSHA256();
|
|
extern bool CPU_ProbeSHA512();
|
|
extern bool CPU_ProbeDARN();
|
|
|
|
// Linux define values from 64-Bit ELF V2 ABI Specification.
|
|
// http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/ch_preface.html
|
|
#ifndef PPC_FEATURE_HAS_ALTIVEC
|
|
# define PPC_FEATURE_HAS_ALTIVEC 0x10000000
|
|
#endif
|
|
#ifndef PPC_FEATURE_ARCH_2_06
|
|
# define PPC_FEATURE_ARCH_2_06 0x00000100
|
|
#endif
|
|
#ifndef PPC_FEATURE2_ARCH_2_07
|
|
# define PPC_FEATURE2_ARCH_2_07 0x80000000
|
|
#endif
|
|
#ifndef PPC_FEATURE2_ARCH_3_00
|
|
# define PPC_FEATURE2_ARCH_3_00 0x00800000
|
|
#endif
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#ifndef PPC_FEATURE2_VEC_CRYPTO
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# define PPC_FEATURE2_VEC_CRYPTO 0x02000000
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#endif
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// AIX defines. We used to just call __power_7_andup()
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// and friends but at Power9, too many compilers were
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// missing __power_9_andup(). Instead we switched to
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// a pattern similar to OpenSSL caps testing.
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#ifndef __power_6_andup
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# define __power_6_andup() __power_set(0xffffffffU<<14)
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#endif
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#ifndef __power_7_andup
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# define __power_7_andup() __power_set(0xffffffffU<<15)
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#endif
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#ifndef __power_8_andup
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# define __power_8_andup() __power_set(0xffffffffU<<16)
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#endif
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#ifndef __power_9_andup
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# define __power_9_andup() __power_set(0xffffffffU<<17)
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#endif
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// AIX first supported Altivec at Power6, though it
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// was available much earlier for other vendors.
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inline bool CPU_QueryAltivec()
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{
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_6_andup() != 0)
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return true;
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#elif defined(__APPLE__) && defined(__POWERPC__)
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unsigned int device, version;
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GetAppleMachineInfo(device, version);
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return device == PowerMac;
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#endif
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return false;
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}
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inline bool CPU_QueryPower7()
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{
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// Power7 and ISA 2.06
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP) & PPC_FEATURE_ARCH_2_06) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_7_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QueryPower8()
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{
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// Power8 and ISA 2.07 provide in-core crypto.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_ARCH_2_07) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_8_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QueryPower9()
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{
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// Power9 and ISA 3.0.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_ARCH_3_00) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_9_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QueryAES()
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{
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// Power8 and ISA 2.07 provide in-core crypto. Glibc
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// 2.24 or higher is required for PPC_FEATURE2_VEC_CRYPTO.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_VEC_CRYPTO) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_8_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QueryPMULL()
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{
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// Power8 and ISA 2.07 provide in-core crypto. Glibc
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// 2.24 or higher is required for PPC_FEATURE2_VEC_CRYPTO.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_VEC_CRYPTO) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_8_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QuerySHA256()
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{
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// Power8 and ISA 2.07 provide in-core crypto. Glibc
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// 2.24 or higher is required for PPC_FEATURE2_VEC_CRYPTO.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_VEC_CRYPTO) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_8_andup() != 0)
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return true;
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#endif
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return false;
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}
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inline bool CPU_QuerySHA512()
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{
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// Power8 and ISA 2.07 provide in-core crypto. Glibc
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// 2.24 or higher is required for PPC_FEATURE2_VEC_CRYPTO.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_VEC_CRYPTO) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_8_andup() != 0)
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return true;
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#endif
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return false;
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}
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// Power9 random number generator
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inline bool CPU_QueryDARN()
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{
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// Power9 and ISA 3.0 provide DARN.
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#if defined(__linux__)
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if ((getauxval(AT_HWCAP2) & PPC_FEATURE2_ARCH_3_00) != 0)
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return true;
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#elif defined(_AIX)
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if (__power_9_andup() != 0)
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return true;
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#endif
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return false;
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}
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void DetectPowerpcFeatures()
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{
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// The CPU_ProbeXXX's return false for OSes which
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// can't tolerate SIGILL-based probes, like Apple
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g_hasAltivec = CPU_QueryAltivec() || CPU_ProbeAltivec();
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g_hasPower7 = CPU_QueryPower7() || CPU_ProbePower7();
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g_hasPower8 = CPU_QueryPower8() || CPU_ProbePower8();
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g_hasPower9 = CPU_QueryPower9() || CPU_ProbePower9();
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g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();
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g_hasAES = CPU_QueryAES() || CPU_ProbeAES();
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g_hasSHA256 = CPU_QuerySHA256() || CPU_ProbeSHA256();
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g_hasSHA512 = CPU_QuerySHA512() || CPU_ProbeSHA512();
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g_hasDARN = CPU_QueryDARN() || CPU_ProbeDARN();
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#if defined(_AIX) && defined(SC_L1C_DLS)
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// /usr/include/sys/systemcfg.h
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int cacheLineSize = getsystemcfg(SC_L1C_DLS);
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if (cacheLineSize > 0)
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g_cacheLineSize = cacheLineSize;
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#elif defined(__linux__) && defined(_SC_LEVEL1_DCACHE_LINESIZE)
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// Glibc does not implement on some platforms. The runtime returns 0 instead of error.
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// https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/posix/sysconf.c
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int cacheLineSize = sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
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if (cacheLineSize > 0)
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g_cacheLineSize = cacheLineSize;
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#endif
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*const_cast<volatile bool*>(&g_PowerpcDetectionDone) = true;
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}
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#endif
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NAMESPACE_END
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// *************************** C++ Static Initialization ***************************
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ANONYMOUS_NAMESPACE_BEGIN
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class InitCpu
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{
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public:
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InitCpu()
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{
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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CryptoPP::DetectX86Features();
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#elif CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8
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CryptoPP::DetectArmFeatures();
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#elif CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64
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CryptoPP::DetectPowerpcFeatures();
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#endif
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}
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};
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// This is not really needed because HasSSE() and friends can dynamically initialize.
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// Everything depends on CPU features so we initialize it once at load time.
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// Dynamic initialization will be used if init priorities are not available.
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#if HAVE_GCC_INIT_PRIORITY
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const InitCpu s_init __attribute__ ((init_priority (CRYPTOPP_INIT_PRIORITY + 10))) = InitCpu();
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#elif HAVE_MSC_INIT_PRIORITY
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#pragma warning(disable: 4075)
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#pragma init_seg(".CRT$XCU")
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const InitCpu s_init;
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#pragma warning(default: 4075)
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#elif HAVE_XLC_INIT_PRIORITY
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// XLC needs constant, not a define
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#pragma priority(270)
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const InitCpu s_init;
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#else
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const InitCpu s_init;
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#endif
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ANONYMOUS_NAMESPACE_END
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#endif // CRYPTOPP_IMPORTS
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