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regs

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julianb0 2019-07-01 00:45:08 +02:00
parent c79ade6609
commit 094c61954d
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GPG Key ID: DDF8325C95299A62
11 changed files with 346 additions and 225 deletions
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162
as/regs.lst
View File

@ -1,51 +1,11 @@
inv
flg
rip
rpc
flg
rx1
rx2
rbp
rsp
rax
rbx
rcx
rdx
rsx
rbi
rsi
rdi
nx0
nx1
nx2
nx3
nx4
nx5
nx6
nx7
ax0
ax1
ax2
ax3
ax4
ax5
ax6
ax7
lx0
lx1
lx2
lx3
lx4
lx5
lx6
lx7
cr0
cr1
cr2
cr3
cr4
cr5
cr6
cr7
px0
px1
fc1
fx2
sa0
sa1
sa2
@ -54,3 +14,115 @@ sa4
sa5
sa6
sa7
dr0
dr1
dr2
dr3
dr4
dr5
dr6
dr7
cr0
cr1
cr2
cr3
cr4
cr5
cr6
cr7
rax
rbx
rcx
rdx
rsi
rdi
rbp
rsp
rx8
rx9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
ax0
ax1
ax2
ax3
ax4
ax5
ax6
ax7
ax8
ax9
a10
a11
a12
a13
a14
a15
a16
a17
a18
a19
a20
a21
a22
a23
a24
a25
a26
a27
a28
a29
a30
a31
nx0
nx1
nx2
nx3
nx4
nx5
nx6
nx7
nx8
nx9
n10
n11
n12
n13
n14
n15
n16
n17
n18
n19
n20
n21
n22
n23
n24
n25
n26
n27
n28
n29
n30
n31

16
ka/ABI
View File

@ -73,7 +73,7 @@ Aside from the DF flag, a function cannot assume anything about the state
of the flags in the FLG register.
Passing parameters is done using the following registers, in that order:
ax0-ax7, lx0-lx7
ax0-ax9, a10-a31
The stack is never used for argument passing, except for variadic functions,
cf the next section. If you need to pass large structures of data, pass
@ -81,14 +81,14 @@ their address in an appropriate register.
Return values are passed in 'rax'. If the return value does not fit
and require more registers, use the following registers, in that order:
rax, rdx, lx0-lx7
rax, rdx, r24-r31
The following registers are volatile; the calling function cannot assume
that they will be left unmodified by the called function:
rax, rcx, rdx, rsx, lx0-lx7, ax0-ax7
rax, rcx, rdx, rx8-r31, ax0-a31
The following registers are nonvolatile; the called function must preserve them:
rbx, rsi, rdi, rbi, nx0-nx7, rbp, rsp
rbx, rsi, rdi, nx0-n31, rbp, rsp
#------------------------------------------------------------------------------#
@ -125,14 +125,16 @@ The 'inv' register cannot be referenced by machine code except when specified
as an offset register in the [reg+reg(*/+...)] memory formats; in these case,
'inv' can be assumed to be always null.
The following registers can only be used by the supervisor; they are intended
to be used as fast global variables for the supervisor:
The following registers can only be used by the supervisor:
- Fast global variables for the supervisor:
sa0-sa7
- Debugging registers for the supervisor:
dr0-dr7
The following registers cannot be referenced by machine code at all; they must
be manipulated through specific instructions, and manipulating their values
allow for controlling the machine in various ways:
cr0-cr7
px0-px1, fc0-fc2, cr0-cr7
#------------------------------------------------------------------------------#

20
ka/crt/fmt/ltostr.k
View File

@ -20,7 +20,7 @@ utoa:
;
ltostr:
mov rax, ax0
xor lx0, lx0
xor rx8, rx8
; make sure base is in [2, 32]
cmp ax2, 2
@ -38,9 +38,9 @@ ltostr:
cmp.nz ax2, 10 ; base 10
j.nz .conv
sgn lx0, ax1 ; extract ax1 sign
sgn rx8, ax1 ; extract ax1 sign
cmp lx0, -1 ; negative?
cmp rx8, -1 ; negative?
neg.z ax1
; main loop
@ -48,20 +48,20 @@ ltostr:
test ax1, ax1
j.z .fini
mov lx1, ax1
rem lx1, ax2 ; ax1 % base
mov r10, ax1
rem r10, ax2 ; ax1 % base
cmp lx1, 9 ; lx1 > 9 ?
cmp r10, 9 ; r10 > 9 ?
j.a .nondec
add lx1, '0'
add r10, '0'
jmp .next
.nondec:
add lx1, 55 ; 'A' - 10
add r10, 55 ; 'A' - 10
.next:
mov b[ax0], lx1
mov b[ax0], r10
inc ax0
div ax1, ax2
@ -69,7 +69,7 @@ ltostr:
; add minus flag, null-terminate and reverse
.fini:
cmp lx0, -1
cmp rx8, -1
mov.z b[ax0], '-'
inc.z ax0

32
ka/crt/fmt/strtol.k
View File

@ -51,14 +51,14 @@ strtoq:
; signed?
test ax2, ax2
sub.z lx1, lx1
sub.z r10, r10
jmp.z .unsigned
; parse '-'
cmp b[rdx], '-'
inc.z rdx
mov.z lx1, 1
sub.nz lx1, lx1
mov.z r10, 1
sub.nz r10, r10
.unsigned:
; base 0
@ -126,38 +126,38 @@ strtoq:
mov ax1, 8
.main_loop:
mov lx0, b[rdx]
mov rx8, b[rdx]
inc rdx
cmp lx0, '0'
cmp rx8, '0'
jmp.b .done
cmp.ae lx0, '9'
sub.be lx0, '0'
cmp.ae rx8, '9'
sub.be rx8, '0'
jmp.be .next
cmp lx0, 'A'
cmp.ae lx0, 'Z'
sub.be lx0, 55 ; 'A' - 10
cmp rx8, 'A'
cmp.ae rx8, 'Z'
sub.be rx8, 55 ; 'A' - 10
jmp.be .next
cmp lx0, 'a'
cmp rx8, 'a'
jmp.b .next
cmp.ae lx0, 'z'
sub.be lx0, 87 ; 'a' - 10
cmp.ae rx8, 'z'
sub.be rx8, 87 ; 'a' - 10
jmp.be .next
.next:
; too large for base?
cmp lx0, ax1
cmp rx8, ax1
jmp.ae .done
mul rax, ax1
add rax, lx0
add rax, rx8
jmp .main_loop
.done:
; negative?
test lx1, lx1
test r10, r10
ret.z
; yes

4
ka/crt/str/strrev.k
View File

@ -12,7 +12,7 @@ strrev:
ret.z
; save str's location
mov lx0, ax1
mov rx8, ax1
; go to str's end, just before
; the null terminator
@ -25,7 +25,7 @@ strrev:
; and forward through buf
mov b[ax0], b[ax1]
cmp ax1, lx0
cmp ax1, rx8
mov.z b[ax0+1], 0
ret.z

22
ka/sys/tests.k
View File

@ -64,15 +64,15 @@ strtol_test:
.s4 = "-1"
speed_test:
utime lx0
utime rx8
mov rcx, ax0
nop.rep
utime lx1
utime rx9
mov rax, lx1
sub rax, lx0
mov rax, rx9
sub rax, rx8
ret
@ -174,8 +174,8 @@ bswap_test:
mov rdx, 0x1122334455667788
bswap rax, rdx
mov rdi, 0x1111222233334444
wswap rsx, rdi
mov rsi, 0x1111222233334444
wswap rx9, rsi
mov ax3, 0x1111111122222222
dswap ax0, ax3
@ -199,10 +199,10 @@ movzx_test:
mov rcx, l[rsp]
mov rdx, q[rsp]
movzx rsx, b[rsp]
movzx rbi, w[rsp]
movzx rsi, l[rsp]
movzx rdi, q[rsp]
movzx rsi, b[rsp]
movzx rdi, w[rsp]
movzx rx8, l[rsp]
movzx rx9, q[rsp]
leave
ret
@ -272,7 +272,7 @@ str_test:
mov ax0, .buf2
mov ax1, .msg
call strcmp
mov rsx, rax
mov r13, rax
mov ax0, .buf2
call strlen

16
vm/dv/cpudev.c
View File

@ -157,14 +157,14 @@ long cpudev_loadargs(ctx_t *ctx, dev_t *dev)
{
CHK_FRAME(ax0);
ax7 = rfs[ax0][AX7];
ax6 = rfs[ax0][AX6];
ax5 = rfs[ax0][AX5];
ax4 = rfs[ax0][AX4];
ax3 = rfs[ax0][AX3];
ax2 = rfs[ax0][AX2];
ax1 = rfs[ax0][AX1];
ax0 = rfs[ax0][AX0];
R(AX7) = rfs[ax0][AX7];
R(AX6) = rfs[ax0][AX6];
R(AX5) = rfs[ax0][AX5];
R(AX4) = rfs[ax0][AX4];
R(AX3) = rfs[ax0][AX3];
R(AX2) = rfs[ax0][AX2];
R(AX1) = rfs[ax0][AX1];
R(AX0) = rfs[ax0][AX0];
return 0;

7
vm/in/misc.c
View File

@ -56,15 +56,14 @@ IMPL_OUT;
IMPL_START_0(clr)
{
rax = rbx = rcx = rdx = 0;
rsx = rbi = rdi = rsi = 0;
rax = rbx = rcx = rdx = rdi = rsi = 0;
}
IMPL_END;
IMPL_START_0(cla)
{
ax0 = ax1 = ax2 = ax3 = 0;
ax4 = ax5 = ax6 = ax7 = 0;
for (int i = AX0; i < AX8; i++)
R(i) = 0;
}
IMPL_END;

5
vm/in/mov.c
View File

@ -53,12 +53,9 @@ IMPL_OUT;
IMPL_START_2(ldarg)
{
if (v2 < 8)
if (v2 < 32)
v1 = R(AX0 + v2);
else if (v2 < 16)
v1 = R(LX0 + v2 - 8);
else
_except(ctx, E_ILL, "ldarg: value out of range: %lu", v1);
}

186
vm/pc/regs.c
View File

@ -6,51 +6,29 @@
reg_t arch_r[] =
{
{ "inv", RES },
{ "rip", RES },
{ "rpc", RES },
{ "flg", RES },
{ "rx1", RES },
{ "rx2", RES },
{ "rbp", GPR },
{ "rsp", GPR },
{ "rax", GPR },
{ "rbx", GPR },
{ "rcx", GPR },
{ "rdx", GPR },
{ "rsx", GPR },
{ "rbi", GPR },
{ "rsi", GPR },
{ "rdi", GPR },
{ "nx0", GPR },
{ "nx1", GPR },
{ "nx2", GPR },
{ "nx3", GPR },
{ "nx4", GPR },
{ "nx5", GPR },
{ "nx6", GPR },
{ "nx7", GPR },
{ "ax0", GPR },
{ "ax1", GPR },
{ "ax2", GPR },
{ "ax3", GPR },
{ "ax4", GPR },
{ "ax5", GPR },
{ "ax6", GPR },
{ "ax7", GPR },
{ "lx0", GPR },
{ "lx1", GPR },
{ "lx2", GPR },
{ "lx3", GPR },
{ "lx4", GPR },
{ "lx5", GPR },
{ "lx6", GPR },
{ "lx7", GPR },
{ "rip", GPR },
{ "rpc", GPR },
{ "px0", CTL },
{ "px1", CTL },
{ "fc1", RES },
{ "fc2", RES },
{ "sa0", SYS },
{ "sa1", SYS },
{ "sa2", SYS },
{ "sa3", SYS },
{ "sa4", SYS },
{ "sa5", SYS },
{ "sa6", SYS },
{ "sa7", SYS },
{ "dr0", SYS },
{ "dr1", SYS },
{ "dr2", SYS },
{ "dr3", SYS },
{ "dr4", SYS },
{ "dr5", SYS },
{ "dr6", SYS },
{ "dr7", SYS },
{ "cr0", CTL },
{ "cr1", CTL },
{ "cr2", CTL },
@ -60,16 +38,109 @@ reg_t arch_r[] =
{ "cr6", CTL },
{ "cr7", CTL },
{ "sa0", SYS },
{ "sa1", SYS },
{ "sa2", SYS },
{ "sa3", SYS },
{ "sa4", SYS },
{ "sa5", SYS },
{ "sa6", SYS },
{ "sa7", SYS },
{ "rax", GPR },
{ "rbx", GPR },
{ "rcx", GPR },
{ "rdx", GPR },
{ "rsi", GPR },
{ "rdi", GPR },
{ "rbp", GPR },
{ "rsp", GPR },
{ "rx8", GPR },
{ "rx9", GPR },
{ "r10", GPR },
{ "r11", GPR },
{ "r12", GPR },
{ "r13", GPR },
{ "r14", GPR },
{ "r15", GPR },
{ "r16", GPR },
{ "r17", GPR },
{ "r18", GPR },
{ "r19", GPR },
{ "r20", GPR },
{ "r21", GPR },
{ "r22", GPR },
{ "r23", GPR },
{ "r24", GPR },
{ "r25", GPR },
{ "r26", GPR },
{ "r27", GPR },
{ "r28", GPR },
{ "r29", GPR },
{ "r30", GPR },
{ "r31", GPR },
{ "ax0", GPR },
{ "ax1", GPR },
{ "ax2", GPR },
{ "ax3", GPR },
{ "ax4", GPR },
{ "ax5", GPR },
{ "ax6", GPR },
{ "ax7", GPR },
{ "ax8", GPR },
{ "ax9", GPR },
{ "a10", GPR },
{ "a11", GPR },
{ "a12", GPR },
{ "a13", GPR },
{ "a14", GPR },
{ "a15", GPR },
{ "a16", GPR },
{ "a17", GPR },
{ "a18", GPR },
{ "a19", GPR },
{ "a20", GPR },
{ "a21", GPR },
{ "a22", GPR },
{ "a23", GPR },
{ "a24", GPR },
{ "a25", GPR },
{ "a26", GPR },
{ "a27", GPR },
{ "a28", GPR },
{ "a29", GPR },
{ "a30", GPR },
{ "a31", GPR },
{ "nx0", GPR },
{ "nx1", GPR },
{ "nx2", GPR },
{ "nx3", GPR },
{ "nx4", GPR },
{ "nx5", GPR },
{ "nx6", GPR },
{ "nx7", GPR },
{ "nx8", GPR },
{ "nx9", GPR },
{ "n10", GPR },
{ "n11", GPR },
{ "n12", GPR },
{ "n13", GPR },
{ "n14", GPR },
{ "n15", GPR },
{ "n16", GPR },
{ "n17", GPR },
{ "n18", GPR },
{ "n19", GPR },
{ "n20", GPR },
{ "n21", GPR },
{ "n22", GPR },
{ "n23", GPR },
{ "n24", GPR },
{ "n25", GPR },
{ "n26", GPR },
{ "n27", GPR },
{ "n28", GPR },
{ "n29", GPR },
{ "n30", GPR },
{ "n31", GPR },
};
static_assert(NREGS <= 256, "");
static_assert(sizeof(arch_r)/sizeof(reg_t) == NREGS, "");
#define DUMPREGS(down, up) \
for (i = down; i <= up; i++) { \
if (i % 4 == 0) \
@ -85,12 +156,13 @@ void dumpregs(ctx_t *ctx)
trace("Current RFRAME index: #%lu\n", rfs_current_idx);
DUMPREGS(RAX, RDI);
DUMPREGS(LX0, LX7);
DUMPREGS(RAX, R15);
trace("\n");
DUMPREGS(NX0, NX7);
DUMPREGS(AX0, AX7);
DUMPREGS(AX0, A15);
trace("\n");
DUMPREGS(NX0, N15);
trace("\n");
DUMPREGS(SA0, SA7);
@ -100,7 +172,7 @@ void dumpregs(ctx_t *ctx)
trace("\n\nrip=0x%-16lX rpc=0x%-16lX rsp=0x%-16lX rbp=0x%-16lX",
rip, rpc, rsp, rbp);
trace("\nrx0=0d%-16lu rx1=0d%-16lu rx2=0d%-16lu flg=0x%-16lX",
trace("\nfc0=0d%-16lu fc1=0d%-16lu fc2=0d%-16lu flg=0x%-16lX",
rx0, rx1, rx2, flg);
trace("\n\nCF=%x OF=%x\n"

101
vm/pc/regs.h
View File

@ -41,71 +41,50 @@ struct reg_t
enum
{
INV, RIP, RPC, FLG,
RX1, RX2, RBP, RSP,
#define inv R(INV)
#define rip R(RIP)
#define rpc R(RPC)
#define flg R(FLG)
#define rx1 R(RX1)
#define rx2 R(RX2)
#define rbp R(RBP)
#define rsp R(RSP)
INV, FLG, RIP, RPC, PX0, PX1, FC1, FC2,
SA0, SA1, SA2, SA3, SA4, SA5, SA6, SA7,
DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7,
CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7,
RAX, RBX, RCX, RDX,
RSX, RBI, RSI, RDI,
#define rax R(RAX)
#define rbx R(RBX)
#define rcx R(RCX)
#define rdx R(RDX)
#define rsx R(RSX)
#define rbi R(RBI)
#define rsi R(RSI)
#define rdi R(RDI)
RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP,
RX8, RX9, R10, R11, R12, R13, R14, R15,
R16, R17, R18, R19, R20, R21, R22, R23,
R24, R25, R26, R27, R28, R29, R30, R31,
NX0, NX1, NX2, NX3,
NX4, NX5, NX6, NX7,
#define nx0 R(NX0)
#define nx1 R(NX1)
#define nx2 R(NX2)
#define nx3 R(NX3)
AX0, AX1, AX2, AX3, AX4, AX5, AX6, AX7,
AX8, AX9, A10, A11, A12, A13, A14, A15,
A16, A17, A18, A19, A20, A21, A22, A23,
A24, A25, A26, A27, A28, A29, A30, A31,
AX0, AX1, AX2, AX3,
AX4, AX5, AX6, AX7,
#define ax0 R(AX0)
#define ax1 R(AX1)
#define ax2 R(AX2)
#define ax3 R(AX3)
#define ax4 R(AX4)
#define ax5 R(AX5)
#define ax6 R(AX6)
#define ax7 R(AX7)
LX0, LX1, LX2, LX3,
LX4, LX5, LX6, LX7,
#define lx0 R(LX0)
#define lx1 R(LX1)
#define lx2 R(LX2)
#define lx3 R(LX3)
#define lx4 R(LX4)
#define lx5 R(LX5)
#define lx6 R(LX6)
#define lx7 R(LX7)
CR0, CR1, CR2, CR3,
CR4, CR5, CR6, CR7,
#define cr0 R(CR0)
#define cr1 R(CR1)
#define cr2 R(CR2)
#define cr3 R(CR3)
SA0, SA1, SA2, SA3,
SA4, SA5, SA6, SA7,
#define sa0 R(SA0)
#define sa1 R(SA1)
#define sa2 R(SA2)
#define sa3 R(SA3)
NX0, NX1, NX2, NX3, NX4, NX5, NX6, NX7,
NX8, NX9, N10, N11, N12, N13, N14, N15,
N16, N17, N18, N19, N20, N21, N22, N23,
N24, N25, N26, N27, N28, N29, N30, N31,
NREGS
};
#define inv R(INV)
#define rip R(RIP)
#define rpc R(RPC)
#define flg R(FLG)
#define rx1 R(FC1)
#define rx2 R(FC2)
#define cr0 R(CR0)
#define cr1 R(CR1)
#define cr2 R(CR2)
#define rax R(RAX)
#define rbx R(RBX)
#define rcx R(RCX)
#define rdx R(RDX)
#define rsi R(RSI)
#define rdi R(RDI)
#define rbp R(RBP)
#define rsp R(RSP)
#define ax0 R(AX0)
#define ax1 R(AX1)
#define ax2 R(AX2)
#define ax3 R(AX3)