os-k-team/kvisc
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stuff

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This commit is contained in:
julianb0 2019-05-29 19:00:13 +02:00
parent f6012cee97
commit 50a76cb490
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GPG Key ID: DDF8325C95299A62
8 changed files with 96 additions and 123 deletions
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10
Makefile
View File

@ -7,14 +7,14 @@ all: kas
kpc:
@cd pc && make --no-print-directory
kas: kpc as/k-as.py as/regs.lst as/testfile.asm
kas: kpc as/k-as.py as/regs.lst as/testfile.k
@cp pc/instrs/instrs.lst as
@rm -f pc/instrs/instrs.lst
test: kas
@cd as && ./k-as.py testfile.asm 0x100000 testout.out
@pc/k.exe as/testout.out
@cd as && ./k-as.py testfile.k 0x100000 testfile.out
@pc/k.exe as/testfile.out
disasm: kas
@cd as && ./k-as.py testfile.asm 0x100000 testout.out
@pc/k.exe as/testout.out -d
@cd as && ./k-as.py testfile.k 0x100000 testfile.out
@pc/k.exe as/testfile.out -d

6
as/k-as.py
View File

@ -13,9 +13,9 @@ if len(sys.argv) != 4:
.format(sys.argv[0]))
sys.exit(1)
instrs = open("{}.instr".format(sys.argv[3]), "w+")
b_data = open("{}.data".format(sys.argv[3]), "w+b")
b_text = open("{}.text".format(sys.argv[3]), "w+b")
instrs = open(".{}.instr".format(sys.argv[3]), "w+")
b_data = open(".{}.data".format(sys.argv[3]), "w+b")
b_text = open(".{}.text".format(sys.argv[3]), "w+b")
lst_regs = open("regs.lst")
lst_instrs = open("instrs.lst")

BIN
as/k-as.py.text
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Binary file not shown.

10
as/testfile.asm → as/testfile.k
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@ -7,16 +7,16 @@ hw = 'Hello World'
; Entry point
;
main:
; This comment is successfully ignored
; Initializes the stack
mov rbp, 0x200000
mov rsp, rbp
mov ax0, hw
call print
mov ax0, hw
mov ax1, hw_len
call print_n
; mov ax0, hw
; mov ax1, hw_len
; call print_n
stop

4
pc/instrs/instrs.c
View File

@ -32,7 +32,9 @@ IMPL_OUT;
IMPL_START_1(lea)
{
assert(p2->mem);
if (!p2->mem) {
_except(ctx, E_ILL, "Bad LEA format");
}
v1 = (p2->type == A_REG ? ctx->r[p2->val].val : p2->val) + p2->off;
}

2
pc/instrs/instrs.h
View File

@ -41,7 +41,7 @@ void i_##name(ctx_t *ctx, acc_t *p1, acc_t *p2) \
#define CHK_SUPERV() \
do { \
if ((ctx->r[FLG].val & UF) == 1) { \
if ((ctx->r[CR0].val & UF) == 1) { \
_except(ctx, E_SYS, "Supervisor-only INSTR"); \
} \
} while (0)

10
pc/instrs/stack.c
View File

@ -39,7 +39,9 @@ IMPL_END;
IMPL_START_0(enter)
{
CHK_STACK(<);
// We don't CHK_STACK(<) here because ENTER
// (should) always be preceded by a CALL,
// which already checks the stack
PUSH(ctx->r[RBP].val);
ctx->r[RBP].val = ctx->r[RSP].val;
}
@ -47,7 +49,8 @@ IMPL_END;
IMPL_START_0(leave)
{
// Do NOT check stack here!
// Do NOT check stack here
// (it would always fail)
POP(ctx->r[RBP].val);
}
IMPL_END;
@ -65,7 +68,8 @@ IMPL_START_0(popf)
{
CHK_STACK(<=);
CHK_SUPERV(); // XXX
// XXX
CHK_SUPERV();
ctx->r[RSP].val += 8;
ctx->r[FLG].val = readmem64(ctx, ctx->r[RSP].val);

177
pc/mem.c
View File

@ -14,75 +14,6 @@ ulong readmem(ctx_t *ctx, ulong addr, uint len)
}
}
ulong readmem8(ctx_t *ctx, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr % 2 == 0) return (ulong)ctx->mp[real] & 0xFF;
else return ((ulong)ctx->mp[real] & 0xFF00) >> 8;
}
ulong readmem16(ctx_t *ctx, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(ushort) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
return (ulong)ctx->mp[real];
}
ulong readmem32(ctx_t *ctx, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(uint) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
ulong val = ctx->mp[real++];
val = val | ((ulong)ctx->mp[real] << 16);
return val;
}
ulong readmem64(ctx_t *ctx, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(ulong) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
ulong val = (ulong)ctx->mp[real++];
val = val | ((ulong)ctx->mp[real++] << 16);
val = val | ((ulong)ctx->mp[real++] << 32);
val = val | ((ulong)ctx->mp[real] << 48);
return val;
}
void writemem(ctx_t *ctx, ulong val, ulong addr, uint len)
{
addr += ctx->r[CR2].val;
@ -95,14 +26,71 @@ void writemem(ctx_t *ctx, ulong val, ulong addr, uint len)
}
}
#define CHK_RANGE() \
if (addr < MEMOFF || real >= MEMSIZE) { \
_except(ctx, E_ACC, \
"Invalid MEM access: 0x%012lX (0x%012lX)", addr, real); \
}
#define CHK_ALIGN(type) \
if (addr % alignof(type) > 0) { \
_except(ctx, E_ALI, \
"Non-aligned memory access: 0x%012lX (0x%012lX) by %lu", \
addr, real, alignof(type)); \
}
#define GETREAL() \
addr += ctx->r[CR2].val; \
ulong real = addr2real(addr)
ulong readmem8(ctx_t *ctx, ulong addr)
{
GETREAL();
CHK_RANGE();
if (addr % 2 == 0) return (ulong)ctx->mp[real] & 0xFF;
else return ((ulong)ctx->mp[real] & 0xFF00) >> 8;
}
ulong readmem16(ctx_t *ctx, ulong addr)
{
GETREAL();
CHK_RANGE();
CHK_ALIGN(ushort);
return (ulong)ctx->mp[real];
}
ulong readmem32(ctx_t *ctx, ulong addr)
{
GETREAL();
CHK_RANGE();
CHK_ALIGN(uint);
ulong val = ctx->mp[real++];
val = val | ((ulong)ctx->mp[real] << 16);
return val;
}
ulong readmem64(ctx_t *ctx, ulong addr)
{
GETREAL();
CHK_RANGE();
CHK_ALIGN(ulong);
ulong val = (ulong)ctx->mp[real++];
val = val | ((ulong)ctx->mp[real++] << 16);
val = val | ((ulong)ctx->mp[real++] << 32);
val = val | ((ulong)ctx->mp[real] << 48);
return val;
}
void writemem8(ctx_t *ctx, ulong val, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
GETREAL();
CHK_RANGE();
ushort v = ctx->mp[real];
@ -117,32 +105,18 @@ void writemem8(ctx_t *ctx, ulong val, ulong addr)
void writemem16(ctx_t *ctx, ulong val, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(ushort) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
GETREAL();
CHK_RANGE();
CHK_ALIGN(ushort);
ctx->mp[real] = val & 0xFFFF;
}
void writemem32(ctx_t *ctx, ulong val, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(uint) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
GETREAL();
CHK_RANGE();
CHK_ALIGN(uint);
ctx->mp[real++] = val & 0xFFFF;
ctx->mp[real] = (val >> 16) & 0xFFFF;
@ -150,16 +124,9 @@ void writemem32(ctx_t *ctx, ulong val, ulong addr)
void writemem64(ctx_t *ctx, ulong val, ulong addr)
{
addr += ctx->r[CR2].val;
ulong real = addr2real(addr);
if (addr % alignof(ulong) > 0) {
_except(ctx, E_ALI, "Non-aligned memory access: 0x%012lX (0x%012lX)", addr, real);
}
if (addr < MEMOFF || real >= MEMSIZE) {
_except(ctx, E_ACC, "Invalid MEM access: 0x%012lX (0x%012lX)", addr, real);
}
GETREAL();
CHK_RANGE();
CHK_ALIGN(ulong);
ctx->mp[real++] = val;
ctx->mp[real++] = (val >> 16) & 0xFFFF;