From 5b3527067f5b1996035c1f16ee39ebbf89a9ddfe Mon Sep 17 00:00:00 2001
From: julianb0 <spectral@os-k.eu>
Date: Wed, 15 May 2019 22:18:47 +0200
Subject: [PATCH] stuff

---
 karch/arch.h |  4 ++--
 karch/regs.c | 68 ++++++++++++++++++++++++++--------------------------
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/karch/arch.h b/karch/arch.h
index 60848c7..a2644e3 100644
--- a/karch/arch.h
+++ b/karch/arch.h
@@ -28,7 +28,7 @@ enum
     R08, R09, R10, R11, R12, R13, R14, R15,
     K00, K01, K02, K03, K04, K05, K06, K07,
     CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7,
-    RIP, RFG,
+    RIP, FLG,
 
     NREGS
 };
@@ -104,7 +104,7 @@ void dumpregs(ctx_t *ctx);
 
 static inline void _except(ctx_t *ctx, int code, char *str)
 {
-    log("Exception %d - %s\n", code, str);
+    log("\nException %d - %s\n", code, str);
     dumpregs(ctx);
     exit(code);
 }
diff --git a/karch/regs.c b/karch/regs.c
index 2aa379e..5fbe145 100644
--- a/karch/regs.c
+++ b/karch/regs.c
@@ -5,39 +5,39 @@
 
 reg_t arch_r[NREGS] =
 {
-    { "RAX", "Accumulator 0", 0, GPR },
-    { "RBX", "Accumulator 1", 0, GPR },
-    { "RCX", "Accumulator 2", 0, GPR },
-    { "RDX", "Accumulator 3", 0, GPR },
-    { "RDI", "Accumulator 4", 0, GPR },
-    { "RSI", "Accumulator 5", 0, GPR },
-    { "RBP", "Stack base",    0, GPR },
-    { "RSP", "Stack pointer", 0, GPR },
-    { "R08", "Accumulator 8", 0, GPR },
-    { "R09", "Accumulator 9", 0, GPR },
-    { "R10", "Accumulator 10", 0, GPR },
-    { "R11", "Accumulator 11", 0, GPR },
-    { "R12", "Accumulator 12", 0, GPR },
-    { "R13", "Accumulator 13", 0, GPR },
-    { "R14", "Accumulator 14", 0, GPR },
-    { "R15", "Accumulator 15", 0, GPR },
-    { "K00", "Supervisor accumulator 0", 0, SYS },
-    { "K01", "Supervisor accumulator 1", 0, SYS },
-    { "K02", "Supervisor accumulator 2", 0, SYS },
-    { "K03", "Supervisor accumulator 3", 0, SYS },
-    { "K04", "Supervisor accumulator 4", 0, SYS },
-    { "K05", "Supervisor accumulator 5", 0, SYS },
-    { "K06", "Supervisor accumulator 6", 0, SYS },
-    { "K07", "Supervisor accumulator 7", 0, SYS },
-    { "CR0", "Control register 0", 0, CTL },
-    { "CR1", "Control register 1", 0, CTL },
-    { "CR2", "Control register 2", 0, CTL },
-    { "CR3", "Control register 3", 0, CTL },
-    { "CR4", "Control register 4", 0, CTL },
-    { "CR5", "Control register 5", 0, CTL },
-    { "CR6", "Control register 6", 0, CTL },
-    { "CR7", "Control register 7", 0, CTL },
-    { "RIP", "Instruction pointer", 0, RES },
-    { "RFG", "Flags register",      0, RES },
+    { "rax", "Accumulator 0", 0, GPR },
+    { "rbx", "Accumulator 1", 0, GPR },
+    { "rcx", "Accumulator 2", 0, GPR },
+    { "rdx", "Accumulator 3", 0, GPR },
+    { "rdi", "Accumulator 4", 0, GPR },
+    { "rsi", "Accumulator 5", 0, GPR },
+    { "rbp", "Stack base",    0, GPR },
+    { "rsp", "Stack pointer", 0, GPR },
+    { "r08", "Accumulator 8", 0, GPR },
+    { "r09", "Accumulator 9", 0, GPR },
+    { "r10", "Accumulator 10", 0, GPR },
+    { "r11", "Accumulator 11", 0, GPR },
+    { "r12", "Accumulator 12", 0, GPR },
+    { "r13", "Accumulator 13", 0, GPR },
+    { "r14", "Accumulator 14", 0, GPR },
+    { "r15", "Accumulator 15", 0, GPR },
+    { "k00", "Supervisor accumulator 0", 0, SYS },
+    { "k01", "Supervisor accumulator 1", 0, SYS },
+    { "k02", "Supervisor accumulator 2", 0, SYS },
+    { "k03", "Supervisor accumulator 3", 0, SYS },
+    { "k04", "Supervisor accumulator 4", 0, SYS },
+    { "k05", "Supervisor accumulator 5", 0, SYS },
+    { "k06", "Supervisor accumulator 6", 0, SYS },
+    { "k07", "Supervisor accumulator 7", 0, SYS },
+    { "cr0", "Control register 0", 0, CTL },
+    { "cr1", "Control register 1", 0, CTL },
+    { "cr2", "Control register 2", 0, CTL },
+    { "cr3", "Control register 3", 0, CTL },
+    { "cr4", "Control register 4", 0, CTL },
+    { "cr5", "Control register 5", 0, CTL },
+    { "cr6", "Control register 6", 0, CTL },
+    { "cr7", "Control register 7", 0, CTL },
+    { "rip", "Instruction pointer", 0, RES },
+    { "flg", "Flags register",      0, RES },
 };