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regsd

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julianb0 2019-06-14 13:34:24 +02:00
parent 49323d29a9
commit 88cd996041
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7 changed files with 110 additions and 105 deletions
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11
as/regs.lst
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@ -3,6 +3,9 @@ rip
flg flg
rbp rbp
rsp rsp
rx0
rx1
rx2
rax rax
rbx rbx
rcx rcx
@ -27,6 +30,14 @@ ax4
ax5 ax5
ax6 ax6
ax7 ax7
lx0
lx1
lx2
lx3
lx4
lx5
lx6
lx7
cr0 cr0
cr1 cr1
cr2 cr2

1
ka/dos.k
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@ -5,7 +5,6 @@
; Entry point ; Entry point
; ;
_start: _start:
; Initializes the stack
mov rbp, 0x200000 mov rbp, 0x200000
mov rsp, rbp mov rsp, rbp

8
vm/in/INSTRS
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@ -594,14 +594,6 @@ clr
# #
cla cla
#
# Clear base non-volatile registers (CLN)
#
# NX0 = NX1 = NX2 = NX3 = 0
# NX4 = NX5 = NX6 = NX7 = 0
#
cln
#---------------------------------------------------------------------------# #---------------------------------------------------------------------------#
# Deprecated and deleted instruction # # Deprecated and deleted instruction #
#---------------------------------------------------------------------------# #---------------------------------------------------------------------------#

7
vm/in/instrs.c
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@ -72,12 +72,5 @@ IMPL_START_0(cla)
} }
IMPL_END; IMPL_END;
IMPL_START_0(cln)
{
nx0 = nx1 = nx2 = nx3 = 0;
nx4 = nx5 = nx6 = nx7 = 0;
}
IMPL_END;
//----------------------------------------------------------------------------// //----------------------------------------------------------------------------//

3
vm/pc/decd.h
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@ -66,7 +66,8 @@ struct acc_t
uint mlen; uint mlen;
// For instruction dumping ONLY // For instruction dumping ONLY
ushort reg1, reg2, imm1, imm2; ushort reg1, reg2;
short imm1, imm2;
}; };
enum { NOPRM, P_REG, P_IMM, P_MEM=4 }; enum { NOPRM, P_REG, P_IMM, P_MEM=4 };

162
vm/pc/regs.c
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@ -5,99 +5,119 @@
reg_t arch_r[NREGS] = reg_t arch_r[NREGS] =
{ {
{ "inv", "Invalid register", "Invalid", 0, RES }, // Invalid register
{ "inv", 0, RES },
{ "rip", "Instruction pointer", "Special; Volatile", 0, RES },
{ "flg", "Flags register", "Special; Volatile", 0, RES }, // Instruction pointer
{ "rip", 0, RES },
// Flags register
{ "flg", 0, RES },
// Stack registers // Stack registers
{ "rbp", "Stack base", "Special; Non-volatile", 0, GPR }, { "rbp", 0, GPR },
{ "rsp", "Stack pointer", "Special; Non-volatile", 0, GPR }, { "rsp", 0, GPR },
// Reserved registers
{ "rx0", 0, RES },
{ "rx1", 0, RES },
{ "rx2", 0, RES },
// General-purpose volatile registers // General-purpose volatile registers
{ "rax", "Accumulator 0", "Volatile", 0, GPR }, { "rax", 0, GPR },
{ "rbx", "Accumulator 1", "Volatile", 0, GPR }, { "rbx", 0, GPR },
{ "rcx", "Accumulator 2", "Volatile", 0, GPR }, { "rcx", 0, GPR },
{ "rdx", "Accumulator 3", "Volatile", 0, GPR }, { "rdx", 0, GPR },
{ "rsx", "Accumulator 4", "Volatile", 0, GPR }, { "rsx", 0, GPR },
{ "rbi", "Accumulator 5", "Volatile", 0, GPR }, { "rbi", 0, GPR },
{ "rdi", "Accumulator 6", "Volatile", 0, GPR }, { "rdi", 0, GPR },
{ "rsi", "Accumulator 7", "Volatile", 0, GPR }, { "rsi", 0, GPR },
// General-purpose non-volatile registers // General-purpose non-volatile registers
{ "nx0", "Accumulator 8", "Non-volatile", 0, GPR }, { "nx0", 0, GPR },
{ "nx1", "Accumulator 9", "Non-volatile", 0, GPR }, { "nx1", 0, GPR },
{ "nx2", "Accumulator 10", "Non-volatile", 0, GPR }, { "nx2", 0, GPR },
{ "nx3", "Accumulator 11", "Non-volatile", 0, GPR }, { "nx3", 0, GPR },
{ "nx4", "Accumulator 12", "Non-volatile", 0, GPR }, { "nx4", 0, GPR },
{ "nx5", "Accumulator 13", "Non-volatile", 0, GPR }, { "nx5", 0, GPR },
{ "nx6", "Accumulator 14", "Non-volatile", 0, GPR }, { "nx6", 0, GPR },
{ "nx7", "Accumulator 15", "Non-volatile", 0, GPR }, { "nx7", 0, GPR },
// Argument registers; volatile // Argument registers; volatile
{ "ax0", "Argument 0", "Volatile", 0, GPR }, { "ax0", 0, GPR },
{ "ax1", "Argument 1", "Volatile", 0, GPR }, { "ax1", 0, GPR },
{ "ax2", "Argument 2", "Volatile", 0, GPR }, { "ax2", 0, GPR },
{ "ax3", "Argument 3", "Volatile", 0, GPR }, { "ax3", 0, GPR },
{ "ax4", "Argument 4", "Volatile", 0, GPR }, { "ax4", 0, GPR },
{ "ax5", "Argument 5", "Volatile", 0, GPR }, { "ax5", 0, GPR },
{ "ax6", "Argument 6", "Volatile", 0, GPR }, { "ax6", 0, GPR },
{ "ax7", "Argument 7", "Volatile", 0, GPR }, { "ax7", 0, GPR },
// cr0: various flags // Leaf function registers; volatile
{ "cr0", "Control register 0", "Control", 0, CTL }, { "lx0", 0, GPR },
{ "lx1", 0, GPR },
{ "lx2", 0, GPR },
{ "lx3", 0, GPR },
{ "lx4", 0, GPR },
{ "lx5", 0, GPR },
{ "lx6", 0, GPR },
{ "lx7", 0, GPR },
// cr1: code offset // Control register
{ "cr1", "Control register 1", "Control", 0, CTL }, { "cr0", 0, CTL },
{ "cr1", 0, CTL },
// cr2: data offset { "cr2", 0, CTL },
{ "cr2", "Control register 2", "Control", 0, CTL }, { "cr3", 0, CTL },
{ "cr4", 0, CTL },
// Unused { "cr5", 0, CTL },
{ "cr3", "Control register 3", "Control", 0, CTL }, { "cr6", 0, CTL },
{ "cr4", "Control register 4", "Control", 0, CTL }, { "cr7", 0, CTL },
{ "cr5", "Control register 5", "Control", 0, CTL },
{ "cr6", "Control register 6", "Control", 0, CTL },
{ "cr7", "Control register 7", "Control", 0, CTL },
// System-reserved // System-reserved
{ "sa0", "Supervisor acc. 0", "System; Non-volatile", 0, SYS }, { "sa0", 0, SYS },
{ "sa1", "Supervisor acc. 1", "System; Non-volatile", 0, SYS }, { "sa1", 0, SYS },
{ "sa2", "Supervisor acc. 2", "System; Non-volatile", 0, SYS }, { "sa2", 0, SYS },
{ "sa3", "Supervisor acc. 3", "System; Non-volatile", 0, SYS }, { "sa3", 0, SYS },
{ "sa4", "Supervisor acc. 4", "System; Non-volatile", 0, SYS }, { "sa4", 0, SYS },
{ "sa5", "Supervisor acc. 5", "System; Non-volatile", 0, SYS }, { "sa5", 0, SYS },
{ "sa6", "Supervisor acc. 6", "System; Non-volatile", 0, SYS }, { "sa6", 0, SYS },
{ "sa7", "Supervisor acc. 7", "System; Non-volatile", 0, SYS }, { "sa7", 0, SYS },
}; };
#define DUMPREGS(down, up) \
for (i = down; i <= up; i++) { \
if (i % 4 == 0) \
log("\n"); \
r = &ctx->r[i]; \
log("%s=0x%-16lX ", r->name, r->val); \
} \
void dumpregs(ctx_t *ctx) void dumpregs(ctx_t *ctx)
{ {
int i; int i;
reg_t *r; reg_t *r;
log("\nRegisters:"); assert(inv == 0);
for (i = RAX; i < CR4; i++) { DUMPREGS(RAX, RSI);
if ((i-1) % 4 == 0) DUMPREGS(AX0, AX3);
log("\n"); DUMPREGS(LX0, LX3);
r = &ctx->r[i]; log("\n");
log("%s%s=0x%-16lX ", r->name, DUMPREGS(NX0, NX3);
(strlen(r->name) == 2 ? "=" : ""), r->val); DUMPREGS(SA0, SA3);
} DUMPREGS(CR0, CR3);
log("\nrip=0x%-16lX rbp=0x%-16lX rsp=0x%-16lX inv=0x%-16lX\n",
rip, rbp, rsp, inv);
log("\nFlags: 0x%-16lX\n", flg); log("\nrip=0x%-16lX rsp=0x%-16lX rbp=0x%-16lX flg=0x%-16lX\n",
rip, rsp, rbp, flg);
log("CF=%-4x OF=%-4x\n" log("\nCF=%-4x OF=%-4x "
"ZF=%-4x SF=%-4x\n" "ZF=%-4x SF=%-4x\n"
"PF=%-4x DF=%-4x\n" "PF=%-4x DF=%-4x "
"IF=%-4x UF=%-4x\n", "IF=%-4x UF=%-4x\n",
!!(flg&CF), !!(flg&OF), !!(flg&CF), !!(flg&OF),
!!(flg&ZF), !!(flg&SF), !!(flg&ZF), !!(flg&SF),
!!(flg&PF), !!(flg&DF), !!(flg&PF), !!(flg&DF),
!!(flg&IF), !!(cr0&UF)); !!(flg&IF), !!(cr0&UF));
} }

23
vm/pc/regs.h
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@ -35,18 +35,17 @@ enum
struct reg_t struct reg_t
{ {
char *name; char *name;
char *desc;
char *conv;
ulong val; ulong val;
ulong flags; ulong flags;
}; };
enum enum
{ {
INV, INV = 0,
#define inv R(INV)
RIP, FLG, RBP, RSP, RIP, FLG, RBP, RSP,
RX0, RX1, RX2,
#define inv R(INV)
#define rip R(RIP) #define rip R(RIP)
#define flg R(FLG) #define flg R(FLG)
#define rbp R(RBP) #define rbp R(RBP)
@ -69,10 +68,6 @@ enum
#define nx1 R(NX1) #define nx1 R(NX1)
#define nx2 R(NX2) #define nx2 R(NX2)
#define nx3 R(NX3) #define nx3 R(NX3)
#define nx4 R(NX4)
#define nx5 R(NX5)
#define nx6 R(NX6)
#define nx7 R(NX7)
AX0, AX1, AX2, AX3, AX0, AX1, AX2, AX3,
AX4, AX5, AX6, AX7, AX4, AX5, AX6, AX7,
@ -85,6 +80,8 @@ enum
#define ax6 R(AX6) #define ax6 R(AX6)
#define ax7 R(AX7) #define ax7 R(AX7)
LX0, LX1, LX2, LX3,
LX4, LX5, LX6, LX7,
CR0, CR1, CR2, CR3, CR0, CR1, CR2, CR3,
CR4, CR5, CR6, CR7, CR4, CR5, CR6, CR7,
@ -92,10 +89,6 @@ enum
#define cr1 R(CR1) #define cr1 R(CR1)
#define cr2 R(CR2) #define cr2 R(CR2)
#define cr3 R(CR3) #define cr3 R(CR3)
#define cr4 R(CR4)
#define cr5 R(CR5)
#define cr6 R(CR6)
#define cr7 R(CR7)
SA0, SA1, SA2, SA3, SA0, SA1, SA2, SA3,
SA4, SA5, SA6, SA7, SA4, SA5, SA6, SA7,
@ -103,10 +96,6 @@ enum
#define sa1 R(SA1) #define sa1 R(SA1)
#define sa2 R(SA2) #define sa2 R(SA2)
#define sa3 R(SA3) #define sa3 R(SA3)
#define sa4 R(SA4)
#define sa5 R(SA5)
#define sa6 R(SA6)
#define sa7 R(SA7)
NREGS NREGS
}; };