// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

#include "arch.h"

reg_t arch_r[NREGS] =
{
    { "rax", "Accumulator 0", 0, GPR },
    { "rbx", "Accumulator 1", 0, GPR },
    { "rcx", "Accumulator 2", 0, GPR },
    { "rdx", "Accumulator 3", 0, GPR },
    { "rdi", "Accumulator 4", 0, GPR },
    { "rsi", "Accumulator 5", 0, GPR },
    { "rbp", "Stack base",    0, GPR },
    { "rsp", "Stack pointer", 0, GPR },
    { "r08", "Accumulator 8", 0, GPR },
    { "r09", "Accumulator 9", 0, GPR },
    { "r10", "Accumulator 10", 0, GPR },
    { "r11", "Accumulator 11", 0, GPR },
    { "r12", "Accumulator 12", 0, GPR },
    { "r13", "Accumulator 13", 0, GPR },
    { "r14", "Accumulator 14", 0, GPR },
    { "r15", "Accumulator 15", 0, GPR },
    { "k00", "Supervisor accumulator 0", 0, SYS },
    { "k01", "Supervisor accumulator 1", 0, SYS },
    { "k02", "Supervisor accumulator 2", 0, SYS },
    { "k03", "Supervisor accumulator 3", 0, SYS },
    { "k04", "Supervisor accumulator 4", 0, SYS },
    { "k05", "Supervisor accumulator 5", 0, SYS },
    { "k06", "Supervisor accumulator 6", 0, SYS },
    { "k07", "Supervisor accumulator 7", 0, SYS },
    { "cr0", "Control register 0", 0, CTL },
    { "cr1", "Control register 1", 0, CTL },
    { "cr2", "Control register 2", 0, CTL },
    { "cr3", "Control register 3", 0, CTL },
    { "cr4", "Control register 4", 0, CTL },
    { "cr5", "Control register 5", 0, CTL },
    { "cr6", "Control register 6", 0, CTL },
    { "cr7", "Control register 7", 0, CTL },
    { "rip", "Instruction pointer", 0, RES },
    { "flg", "Flags register",      0, RES },
    { "ret", "Return address",      0, RES },
};