// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

// Register types
enum
{
    GPR = 1 << 0,   // General
    CTL = 1 << 1,   // Control
    SEG = 1 << 2,   // Segment
    RES = 1 << 8,   // Reserved for insternal use
    SYS = 1 << 9,   // Reserved for supervisor mode
};

// FLG register
enum
{
    CF = 1 << 0,        // Carry flag
    OF = 1 << 1,        // Overflow flag

    ZF = 1 << 2,        // Zero flag
    SF = 1 << 3,        // Sign flag

    PF = 1 << 4,        // Parity flag
    DF = 1 << 5,        // Direction flag

    IF = 1 << 16,       // Interrupts enable flag
};

// CR0 register
enum
{
    UF = 1 << 15,       // User-mode flag
};

struct reg_t
{
    char   *name;
    ulong   val;
    ulong   flags;
};

enum
{
    INV = 0,
    
    RIP, FLG, RBP, RSP,
    RX0, RX1, RX2,
#define inv R(INV)
#define rip R(RIP)
#define flg R(FLG)
#define rbp R(RBP)
#define rsp R(RSP)

    RAX, RBX, RCX, RDX,
    RSX, RBI, RDI, RSI,
#define rax R(RAX)
#define rbx R(RBX)
#define rcx R(RCX)
#define rdx R(RDX)
#define rsx R(RSX)
#define rbi R(RBI)
#define rdi R(RDI)
#define rsi R(RSI)

    NX0, NX1, NX2, NX3,
    NX4, NX5, NX6, NX7,
#define nx0 R(NX0)
#define nx1 R(NX1)
#define nx2 R(NX2)
#define nx3 R(NX3)

    AX0, AX1, AX2, AX3,
    AX4, AX5, AX6, AX7,
#define ax0 R(AX0)
#define ax1 R(AX1)
#define ax2 R(AX2)
#define ax3 R(AX3)
#define ax4 R(AX4)
#define ax5 R(AX5)
#define ax6 R(AX6)
#define ax7 R(AX7)

    LX0, LX1, LX2, LX3,
    LX4, LX5, LX6, LX7,

    CR0, CR1, CR2, CR3,
    CR4, CR5, CR6, CR7,
#define cr0 R(CR0)
#define cr1 R(CR1)
#define cr2 R(CR2)
#define cr3 R(CR3)

    SA0, SA1, SA2, SA3,
    SA4, SA5, SA6, SA7,
#define sa0 R(SA0)
#define sa1 R(SA1)
#define sa2 R(SA2)
#define sa3 R(SA3)

    NREGS
};