// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

#include "arch.h"

reg_t arch_r[NREGS] =
{
    { "inv", "Invalid register", "Invalid", 0, RES },

    { "rip", "Instruction pointer", "Special; Volatile", 0, RES },
    { "flg", "Flags register", "Special; Volatile", 0, RES },

    // Stack registers
    { "rbp", "Stack base",    "Special; Non-volatile", 0, GPR },
    { "rsp", "Stack pointer", "Special; Non-volatile", 0, GPR },

    // General-purpose volatile registers
    { "rax", "Accumulator 0", "Volatile", 0, GPR },
    { "rbx", "Accumulator 1", "Volatile", 0, GPR },
    { "rcx", "Accumulator 2", "Volatile", 0, GPR },
    { "rdx", "Accumulator 3", "Volatile", 0, GPR },
    { "rsx", "Accumulator 4", "Volatile", 0, GPR },
    { "rbi", "Accumulator 5", "Volatile", 0, GPR },
    { "rdi", "Accumulator 6", "Volatile", 0, GPR },
    { "rsi", "Accumulator 7", "Volatile", 0, GPR },

    // General-purpose non-volatile registers
    { "nx0", "Accumulator 8", "Non-volatile", 0, GPR },
    { "nx1", "Accumulator 9", "Non-volatile", 0, GPR },
    { "nx2", "Accumulator 10", "Non-volatile", 0, GPR },
    { "nx3", "Accumulator 11", "Non-volatile", 0, GPR },
    { "nx4", "Accumulator 12", "Non-volatile", 0, GPR },
    { "nx5", "Accumulator 13", "Non-volatile", 0, GPR },
    { "nx6", "Accumulator 14", "Non-volatile", 0, GPR },
    { "nx7", "Accumulator 15", "Non-volatile", 0, GPR },

    // Argument registers; volatile
    { "ax0", "Argument 0", "Volatile", 0, GPR },
    { "ax1", "Argument 1", "Volatile", 0, GPR },
    { "ax2", "Argument 2", "Volatile", 0, GPR },
    { "ax3", "Argument 3", "Volatile", 0, GPR },
    { "ax4", "Argument 4", "Volatile", 0, GPR },
    { "ax5", "Argument 5", "Volatile", 0, GPR },
    { "ax6", "Argument 6", "Volatile", 0, GPR },
    { "ax7", "Argument 7", "Volatile", 0, GPR },

    // cr0: various flags
    { "cr0", "Control register 0", "Control", 0, CTL },
    
    // cr1: code offset
    { "cr1", "Control register 1", "Control", 0, CTL },
    
    // cr2: data offset
    { "cr2", "Control register 2", "Control", 0, CTL },

    // Unused
    { "cr3", "Control register 3", "Control", 0, CTL },
    { "cr4", "Control register 4", "Control", 0, CTL },
    { "cr5", "Control register 5", "Control", 0, CTL },
    { "cr6", "Control register 6", "Control", 0, CTL },
    { "cr7", "Control register 7", "Control", 0, CTL },

    // System-reserved
    { "sa0", "Supervisor acc. 0", "System; Non-volatile", 0, SYS },
    { "sa1", "Supervisor acc. 1", "System; Non-volatile", 0, SYS },
    { "sa2", "Supervisor acc. 2", "System; Non-volatile", 0, SYS },
    { "sa3", "Supervisor acc. 3", "System; Non-volatile", 0, SYS },
    { "sa4", "Supervisor acc. 4", "System; Non-volatile", 0, SYS },
    { "sa5", "Supervisor acc. 5", "System; Non-volatile", 0, SYS },
    { "sa6", "Supervisor acc. 6", "System; Non-volatile", 0, SYS },
    { "sa7", "Supervisor acc. 7", "System; Non-volatile", 0, SYS },
};

void dumpregs(ctx_t *ctx)
{
    int i;
    reg_t *r;
    
    assert(ctx->r[INV].val == 0);
    
    log("\nRegisters:");
    
    for (i = RAX; i < CR4; i++) {
        if ((i-1) % 4 == 0)
            log("\n");
        
        r = &ctx->r[i];
        log("%s%s=0x%-16lX ", r->name,
            (strlen(r->name) == 2 ? "=" : ""), r->val);
    }
    log("\nrip=0x%-16lX rbp=0x%-16lX rsp=0x%-16lX flg=0x%-16lX\n",
        ctx->r[RIP].val,
        ctx->r[RBP].val,
        ctx->r[RSP].val,
        ctx->r[FLG].val);
}