98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
// The OS/K Team licenses this file to you under the MIT license.
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// See the LICENSE file in the project root for more information.
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#include "arch.h"
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reg_t arch_r[NREGS] =
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{
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{ "inv", "Invalid register", "Invalid", 0, RES },
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{ "rip", "Instruction pointer", "Special; Volatile", 0, RES },
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{ "flg", "Flags register", "Special; Volatile", 0, RES },
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// Stack registers
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{ "rbp", "Stack base", "Special; Non-volatile", 0, GPR },
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{ "rsp", "Stack pointer", "Special; Non-volatile", 0, GPR },
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// General-purpose volatile registers
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{ "rax", "Accumulator 0", "Volatile", 0, GPR },
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{ "rbx", "Accumulator 1", "Volatile", 0, GPR },
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{ "rcx", "Accumulator 2", "Volatile", 0, GPR },
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{ "rdx", "Accumulator 3", "Volatile", 0, GPR },
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{ "rsx", "Accumulator 4", "Volatile", 0, GPR },
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{ "rbi", "Accumulator 5", "Volatile", 0, GPR },
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{ "rdi", "Accumulator 6", "Volatile", 0, GPR },
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{ "rsi", "Accumulator 7", "Volatile", 0, GPR },
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// General-purpose non-volatile registers
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{ "nx0", "Accumulator 8", "Non-volatile", 0, GPR },
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{ "nx1", "Accumulator 9", "Non-volatile", 0, GPR },
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{ "nx2", "Accumulator 10", "Non-volatile", 0, GPR },
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{ "nx3", "Accumulator 11", "Non-volatile", 0, GPR },
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{ "nx4", "Accumulator 12", "Non-volatile", 0, GPR },
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{ "nx5", "Accumulator 13", "Non-volatile", 0, GPR },
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{ "nx6", "Accumulator 14", "Non-volatile", 0, GPR },
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{ "nx7", "Accumulator 15", "Non-volatile", 0, GPR },
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// Argument registers; volatile
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{ "ax0", "Argument 0", "Volatile", 0, GPR },
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{ "ax1", "Argument 1", "Volatile", 0, GPR },
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{ "ax2", "Argument 2", "Volatile", 0, GPR },
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{ "ax3", "Argument 3", "Volatile", 0, GPR },
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{ "ax4", "Argument 4", "Volatile", 0, GPR },
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{ "ax5", "Argument 5", "Volatile", 0, GPR },
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{ "ax6", "Argument 6", "Volatile", 0, GPR },
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{ "ax7", "Argument 7", "Volatile", 0, GPR },
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// cr0: various flags
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{ "cr0", "Control register 0", "Control", 0, CTL },
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// cr1: code offset
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{ "cr1", "Control register 1", "Control", 0, CTL },
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// cr2: data offset
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{ "cr2", "Control register 2", "Control", 0, CTL },
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// Unused
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{ "cr3", "Control register 3", "Control", 0, CTL },
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{ "cr4", "Control register 4", "Control", 0, CTL },
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{ "cr5", "Control register 5", "Control", 0, CTL },
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{ "cr6", "Control register 6", "Control", 0, CTL },
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{ "cr7", "Control register 7", "Control", 0, CTL },
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// System-reserved
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{ "sa0", "Supervisor acc. 0", "System; Non-volatile", 0, SYS },
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{ "sa1", "Supervisor acc. 1", "System; Non-volatile", 0, SYS },
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{ "sa2", "Supervisor acc. 2", "System; Non-volatile", 0, SYS },
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{ "sa3", "Supervisor acc. 3", "System; Non-volatile", 0, SYS },
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{ "sa4", "Supervisor acc. 4", "System; Non-volatile", 0, SYS },
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{ "sa5", "Supervisor acc. 5", "System; Non-volatile", 0, SYS },
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{ "sa6", "Supervisor acc. 6", "System; Non-volatile", 0, SYS },
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{ "sa7", "Supervisor acc. 7", "System; Non-volatile", 0, SYS },
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};
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void dumpregs(ctx_t *ctx)
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{
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int i;
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reg_t *r;
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assert(ctx->r[INV].val == 0);
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log("\nRegisters:");
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for (i = RAX; i < CR4; i++) {
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if ((i-1) % 4 == 0)
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log("\n");
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r = &ctx->r[i];
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log("%s%s=0x%-16lX ", r->name,
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(strlen(r->name) == 2 ? "=" : ""), r->val);
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}
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log("\nrip=0x%-16lX rbp=0x%-16lX rsp=0x%-16lX flg=0x%-16lX\n",
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ctx->r[RIP].val,
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ctx->r[RBP].val,
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ctx->r[RSP].val,
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ctx->r[FLG].val);
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}
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