mirror of
https://gitlab.os-k.eu/os-k-team/kvisc.git
synced 2023-08-25 14:05:46 +02:00
396 lines
7.6 KiB
C
396 lines
7.6 KiB
C
// The OS/K Team licenses this file to you under the MIT license.
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// See the LICENSE file in the project root for more information.
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#include <pc/arch.h>
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//
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// Imperatively read the "DECD" file before reading this code
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//
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static void check_param_type(ctx_t *ctx, uint prm, uchar fmt)
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{
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bool ok;
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if (prm == P_REG)
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ok = (fmt == A_REG);
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else if (prm == P_IMM)
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ok = (fmt == A_IMM64);
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else /* if (prm == P_MEM) */
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ok = ACC_FMT_IS_MEM(fmt);
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if (!ok)
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_except(ctx, E_ILL,
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"FT1 or FT2 not matching INSTR's expected parameter types");
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}
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void decode(ctx_t *ctx)
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{
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char *illmsg;
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instr_t *in;
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acc_t p1 = { 0 };
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acc_t p2 = { 0 };
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bool rep = 0
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uint cond = 0;
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bool lock, nomore;
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ushort w1, w2;
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uchar f1 = 0, f2 = 0;
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ulong pc = rip;
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//
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// Process the first word of the instruction
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//
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w1 = ctx->get(ctx);
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// Extract first word flags
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lock = !!(w1 & PREF_LOCK);
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nomore = !!(w1 & PREF_NOMORE);
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w1 &= ~(PREF_LOCK|PREF_NOMORE);
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// Find instruction
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if (w1 >= NINSTRS)
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{
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illmsg = "No such INSTR";
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goto ill;
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}
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in = &ctx->i[w1];
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if (!nomore)
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goto skip_w2;
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//
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// Process second word
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//
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w2 = ctx->get(ctx);
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// REP and COND
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rep = !!(w2 & PREF_REP);
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cond = (w2 & BITS_COND) >> COND_SHIFT;
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// F1 and F2
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f1 = (w2 >> F1_SHIFT) & Fx_MASK;
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f2 = w2 & Fx_MASK;
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skip_w2:
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//
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// Deal with operand 1
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//
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if (in->prm1 == NOPRM)
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{
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if (f1 || f2)
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{
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illmsg = "FT1 and/or FT2 filled for 0-param INSTR";
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goto ill;
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}
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exec_instr(ctx, in, NULL, NULL, lock, rep, cond, pc);
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return;
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}
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check_param_type(ctx, in->prm1, f1);
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extract_param(ctx, &p1, f1);
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//
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// Deal with operand 2
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//
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if (in->prm2 == NOPRM)
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{
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if (f2)
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{
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illmsg = "FT2 filled for 1-param INSTR";
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goto ill;
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}
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exec_instr(ctx, in, &p1, NULL, lock, rep, cond, pc);
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return;
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}
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check_param_type(ctx, in->prm2, f2);
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extract_param(ctx, &p2, f2);
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exec_instr(ctx, in, &p1, &p2, lock, rep, cond, pc);
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return;
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ill:
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_except(ctx, E_ILL, illmsg);
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}
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//
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// Verify that access to a certain register is legal
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//
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static void checkreg(ctx_t *ctx, uint reg, bool inv_is_ok)
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{
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if (reg >= NREGS)
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_except(ctx, E_ILL, "Inexistent register: %u", reg);
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if (reg == INV)
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{
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if (!inv_is_ok)
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_except(ctx, E_ILL, "INV dereference");
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else
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return;
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}
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if (ctx->r[reg].flags & (RES | CTL))
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_except(ctx, E_ACC, "Reserved REG: %u", reg);
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if (ctx->r[reg].flags & SYS)
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if (cr0 & UF)
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_except(ctx, E_SYS, "User access to SYS REG: %u", reg);
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}
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//
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// Extract operand according to fmt
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//
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void extract_param(ctx_t *ctx, acc_t *p, uchar fmt)
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{
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uint mlen, mfmt, reg1, reg2, imm1 = 0, imm2 = 0;
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ushort temp;
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p->type = fmt;
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if (fmt == A_REG)
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{
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p->reg = ctx->get(ctx);
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checkreg(ctx, p->reg, 0);
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p->val = R(p->reg);
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}
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else if (fmt == A_IMM64)
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{
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p->val = ctx->get(ctx);
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p->val |= (ulong)ctx->get(ctx) << 16;
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p->val |= (ulong)ctx->get(ctx) << 32;
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p->val |= (ulong)ctx->get(ctx) << 48;
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}
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assert(ACC_FMT_IS_MEM(fmt));
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//
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// Handle a memory access
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//
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mlen = fmt & AM_MLEN_MASK;
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mfmt = fmt & AM_MFMT_MASK;
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p->mlen = (mlen == AM_8ACC ? 1
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: (mlen == AM_16ACC ? 2
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: (mlen == AM_32ACC ? 4
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: (mlen == AM_64ACC ? 8 : 0))));
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if (p->mlen == 0)
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_except(ctx, E_ILL, "Invalid MLEN for access: %x", fmt);
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switch (mfmt)
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{
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case AM_IMM64:
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p->addr = ctx->get(ctx);
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p->addr |= (ulong)ctx->get(ctx) << 16;
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p->addr |= (ulong)ctx->get(ctx) << 32;
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p->addr |= (ulong)ctx->get(ctx) << 48;
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break;
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case AM_RR:
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case AM_RRI:
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case AM_RRII:
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temp = ctx->get(ctx);
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reg1 = temp >> 8;
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reg2 = temp & 0xFF;
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checkreg(ctx, reg1, 0);
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checkreg(ctx, reg2, 1);
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if (fmt == AM_RRI)
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{
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imm1 = 1;
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imm2 = ctx->get(ctx);
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}
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else if (fmt == AM_RRII)
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{
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imm1 = ctx->get(ctx);
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imm2 = ctx->get(ctx);
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}
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p->addr = R(reg1) + R(reg2) * imm1 + imm2;
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break;
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default:
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_except(ctx, E_ILL, "Invalid MFMT for access: %x", fmt);
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}
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p->val = readmem(ctx, p->addr, p->mlen);
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}
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static bool eval_cond(ctx_t *ctx, uint cond)
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{
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bool neg = cond & (1 << 5);
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bool ok;
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cond &= ~(1 << 5);
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switch (cond)
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{
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case CD_C: ok = flg&CF; break;
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case CD_O: ok = flg&OF; break;
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case CD_Z: ok = flg&ZF; break;
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case CD_S: ok = flg&SF; break;
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case CD_P: ok = flg&PF; break;
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case CD_A: ok = !(flg&CF || flg&ZF); break;
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case CD_AE: ok = !(flg&CF); break;
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case CD_B: ok = flg&CF; break;
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case CD_BE: ok = flg&CF || flg&ZF; break;
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case CD_G: ok = !(flg&ZF) && (!(flg&SF) == !(flg&OF)); break;
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case CD_GE: ok = !(flg&SF) == !(flg&OF); break;
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case CD_L: ok = !(flg&SF) != !(flg&OF); break;
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case CD_LE: ok = flg&ZF || (!(flg&SF) != !(flg&OF)); break;
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case CD_CXZ: ok = !rcx; break;
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default:
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_except(ctx, E_ILL, "Invalid COND value: %x", cond);
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}
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return neg ? !ok : !!ok;
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}
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char *cond_suffixes[] =
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{
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"",
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".c"
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};
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static void dump_acc(ctx_t *ctx, acc_t *p)
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{
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uint mfmt;
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if (p->type == A_REG)
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log("%s", ctx->r[p->reg].name);
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else if (p->type == A_IMM64)
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log("imm64:0x%016lX", p->val);
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else
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{
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log("%c[", getmempref(p->mlen));
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mfmt = p->type & AM_MFMT_MASK;
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if (mfmt == AM_IMM64)
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log("imm64:");
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else if (mfmt == AM_RR)
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log("rr:");
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else if (mfmt == AM_RRI)
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log("rri:");
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else if (mfmt == AM_RRII)
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log("rrii:");
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log("0x%016lX]", p->addr);
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}
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}
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static void dump_instr(
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ctx_t *ctx, instr_t *in,
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acc_t *p1, acc_t *p2,
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bool lock, bool rep,
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uint cond, ulong pc)
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{
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log("0x%016lX: ", pc);
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if (lock)
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log("lock ");
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if (rep)
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log("rep ");
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if (cond)
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log("cond%u ", cond);
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log("%s ", in->full);
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if (p1) {
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dump_acc(ctx, p1);
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if (p2) {
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log(", ");
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dump_acc(ctx, p2);
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}
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}
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log("\n");
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}
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//
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// Executes an instruction
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//
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void exec_instr(
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ctx_t *ctx, instr_t *in,
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acc_t *p1, acc_t *p2,
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bool lock, bool rep,
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uint cond, ulong pc)
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{
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bool out = 0;
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ulong ret = 0;
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// Debugging
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dump_instr(ctx, in, p1, p2, lock, rep, cond, pc);
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if (rep && !cond)
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cond = CD_CXZ;
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do_rep:
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if (!eval_cond(ctx, cond))
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return;
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out = in->func(ctx, p1, p2, &ret);
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if (out)
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{
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if (p1->type == A_REG)
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R(p1->reg) = ret;
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else if (p1->type == A_IMM64)
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_except(ctx, E_ACC, "Trying to output to an IMM64");
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else
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{
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assert(ACC_IS_MEM(p1));
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writemem(ctx, ret, p1->addr, p1->mlen);
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}
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}
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if (rep)
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{
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if (cond == CD_CXZ)
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rcx--;
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goto do_rep;
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}
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}
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