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mirror of https://gitlab.os-k.eu/os-k-team/kvisc.git synced 2023-08-25 14:05:46 +02:00
kvisc/vm/pc/regs.c
2019-07-11 18:34:21 +02:00

55 lines
2.1 KiB
C

// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
#include <pc/device.h>
reg_t arch_r[] =
{
{ "inv", RES }, { "fc1", RES }, { "cr0", SYS }, { "cr1", SYS },
{ "cr2", SYS }, { "cr3", SYS }, { "cr4", SYS }, { "trp", GPR },
{ "rax", GPR }, { "rbx", GPR }, { "rcx", GPR }, { "rdx", GPR },
{ "rsi", GPR }, { "rdi", GPR }, { "rbp", GPR }, { "rsp", GPR },
{ "rfx", GPR }, { "rip", GPR }, { "r10", GPR }, { "r11", GPR },
{ "r12", GPR }, { "r13", GPR }, { "r14", GPR }, { "r15", GPR },
{ "ax0", GPR }, { "ax1", GPR }, { "ax2", GPR }, { "ax3", GPR },
{ "ax4", GPR }, { "ax5", GPR }, { "ax6", GPR }, { "ax7", GPR },
{ "nx0", GPR }, { "nx1", GPR }, { "nx2", GPR }, { "nx3", GPR },
{ "nx4", GPR }, { "nx5", GPR }, { "nx6", GPR }, { "nx7", GPR },
};
static_assert(sizeof(arch_r)/sizeof(reg_t) == NREGS, "");
void dumpregs(ctx_t *ctx)
{
trace("Current RFRAME index: #%lu", rfs_current_idx);
trace("\n\nEnviron:");
trace("\nrpc=0x%-16lX rip=0x%-16lX rfx=0x%-16lX", rpc, R(RIP), R(RFX));
trace("\nrsp=0x%-16lX rbp=0x%-16lX trp=0x%-16lX", R(RSP), R(RBP), R(TRP));
trace("\n\nControl:");
trace("\ncr0=0x%-16lX cr1=0x%-16lX cr2=0x%-16lX", R(CR0), R(CR1), R(CR2));
trace("\nfc0=0d%-16lu fc1=0d%-16lu fc2=0d%-16lu", fc0, fc1, fc2);
trace("\n\nArgument:");
trace("\nax0=0x%-16lX ax1=0x%-16lX ax2=0x%-16lX", R(AX0), R(AX1), R(AX2));
trace("\nax3=0x%-16lX ax4=0x%-16lX ax5=0x%-16lX", R(AX3), R(AX4), R(AX5));
trace("\n\nVolatile:");
trace("\nrax=0x%-16lX rcx=0x%-16lX rdx=0x%-16lX", R(RAX), R(RCX), R(RDX));
trace("\nr10=0x%-16lX r11=0x%-16lX r12=0x%-16lX", R(R10), R(R11), R(R12));
trace("\nr13=0x%-16lX r14=0x%-16lX r15=0x%-16lX", R(R13), R(R14), R(R15));
trace("\n\nPersistent:");
trace("\nrbx=0x%-16lX rdi=0x%-16lX rsi=0x%-16lX", R(RBX), R(RDI), R(RSI));
trace("\nnx0=0x%-16lX nx1=0x%-16lX nx2=0x%-16lX", R(NX0), R(NX1), R(NX2));
trace("\nnx3=0x%-16lX nx4=0x%-16lX nx5=0x%-16lX", R(NX3), R(NX4), R(NX5));
trace("\n");
assert(R(INV) == 0);
}