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mirror of https://gitlab.os-k.eu/os-k-team/kvisc.git synced 2023-08-25 14:05:46 +02:00
kvisc/vm/pc/regs.c
julianb0 d13da7b480
vm
2019-06-14 16:47:01 +02:00

125 lines
2.9 KiB
C

// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
#include <pc/arch.h>
reg_t arch_r[NREGS] =
{
// Invalid register
{ "inv", 0, RES },
// Instruction pointer
{ "rip", 0, RES },
// Flags register
{ "flg", 0, RES },
// Stack registers
{ "rbp", 0, GPR },
{ "rsp", 0, GPR },
// Reserved registers
{ "rx0", 0, RES },
{ "rx1", 0, RES },
{ "rx2", 0, RES },
// General-purpose volatile registers
{ "rax", 0, GPR },
{ "rbx", 0, GPR },
{ "rcx", 0, GPR },
{ "rdx", 0, GPR },
{ "rsx", 0, GPR },
{ "rbi", 0, GPR },
{ "rdi", 0, GPR },
{ "rsi", 0, GPR },
// General-purpose non-volatile registers
{ "nx0", 0, GPR },
{ "nx1", 0, GPR },
{ "nx2", 0, GPR },
{ "nx3", 0, GPR },
{ "nx4", 0, GPR },
{ "nx5", 0, GPR },
{ "nx6", 0, GPR },
{ "nx7", 0, GPR },
// Argument registers; volatile
{ "ax0", 0, GPR },
{ "ax1", 0, GPR },
{ "ax2", 0, GPR },
{ "ax3", 0, GPR },
{ "ax4", 0, GPR },
{ "ax5", 0, GPR },
{ "ax6", 0, GPR },
{ "ax7", 0, GPR },
// Leaf function registers; volatile
{ "lx0", 0, GPR },
{ "lx1", 0, GPR },
{ "lx2", 0, GPR },
{ "lx3", 0, GPR },
{ "lx4", 0, GPR },
{ "lx5", 0, GPR },
{ "lx6", 0, GPR },
{ "lx7", 0, GPR },
// Control register
{ "cr0", 0, CTL },
{ "cr1", 0, CTL },
{ "cr2", 0, CTL },
{ "cr3", 0, CTL },
{ "cr4", 0, CTL },
{ "cr5", 0, CTL },
{ "cr6", 0, CTL },
{ "cr7", 0, CTL },
// System-reserved
{ "sa0", 0, SYS },
{ "sa1", 0, SYS },
{ "sa2", 0, SYS },
{ "sa3", 0, SYS },
{ "sa4", 0, SYS },
{ "sa5", 0, SYS },
{ "sa6", 0, SYS },
{ "sa7", 0, SYS },
};
#define DUMPREGS(down, up) \
for (i = down; i <= up; i++) { \
if (i % 4 == 0) \
log("\n"); \
r = &ctx->r[i]; \
log("%s=0x%-16lX ", r->name, r->val); \
} \
void dumpregs(ctx_t *ctx)
{
int i;
reg_t *r;
assert(inv == 0);
DUMPREGS(RAX, RSI);
DUMPREGS(AX0, AX3);
DUMPREGS(LX0, LX3);
log("\n");
DUMPREGS(NX0, NX3);
DUMPREGS(SA0, SA3);
DUMPREGS(CR0, CR3);
log("\n\nrip=0x%-16lX rsp=0x%-16lX rbp=0x%-16lX flg=0x%-16lX\n\n",
rip, rsp, rbp, flg);
log("CF=%x OF=%x\n"
"ZF=%x SF=%x\n"
"PF=%x DF=%x\n"
"IF=%x UF=%x\n",
!!(flg&CF), !!(flg&OF),
!!(flg&ZF), !!(flg&SF),
!!(flg&PF), !!(flg&DF),
!!(flg&IF), !!(cr0&UF));
}