2019-05-14 14:39:35 +02:00
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#include <kernel.h>
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2019-05-15 15:55:57 +02:00
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#include <init/boot.h>
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2019-05-15 19:11:47 +02:00
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#include <ex/malloc.h>
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#include <mm/mm.h>
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2019-05-18 13:39:58 +02:00
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#include <ke/idt.h>
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2019-05-19 00:07:01 +02:00
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#include <lib/buf.h>
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#include <io/vga.h>
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2019-05-14 14:39:35 +02:00
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enum
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{
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MF_PRESENT = 1 << 0,
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MF_READWRITE = 1 << 1,
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MF_USERMODE = 1 << 2,
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MF_WRITETHR = 1 << 3,
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MF_CACHEDIS = 1 << 4,
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MF_ACCESSED = 1 << 5,
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2019-05-15 11:15:21 +02:00
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MF_DIRTY = 1 << 6,
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2019-05-15 15:55:57 +02:00
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MF_HUGE = 1 << 7,
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MF_NX = 1 << 31
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2019-05-14 14:39:35 +02:00
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};
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2019-05-16 23:56:23 +02:00
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#define RAM_MAX 32
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2019-05-15 19:11:47 +02:00
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#define NB_4K 150
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// * 2 MB
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2019-05-15 02:26:55 +02:00
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2019-05-14 14:39:35 +02:00
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//-----------
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2019-05-18 12:58:54 +02:00
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volatile pdpe_t MmPML4[512] __attribute__((__aligned__(KPAGESIZE)));
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2019-05-14 14:39:35 +02:00
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2019-05-18 12:58:54 +02:00
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volatile pde_t MmPDP[512] __attribute__((__aligned__(KPAGESIZE)));
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2019-05-14 14:39:35 +02:00
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2019-05-18 12:58:54 +02:00
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volatile pde_t MmPD[512 * RAM_MAX] __attribute__((__aligned__(KPAGESIZE)));;
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2019-05-14 14:39:35 +02:00
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2019-05-18 12:58:54 +02:00
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volatile pte_t MmPT[512 * NB_4K] __attribute__((__aligned__(KPAGESIZE)));;
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2019-05-14 14:39:35 +02:00
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2019-12-21 13:55:02 +01:00
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extern ulong _text;
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extern ulong _text_end;
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extern ulong _rodata;
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extern ulong _rodata_end;
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extern ulong _data;
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extern ulong _data_end;
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2019-05-22 00:38:04 +02:00
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ulong MmStackGuards[2] = { 0 };
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2019-05-15 15:55:57 +02:00
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//
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// Creates our new page table structure and loads it
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2019-05-18 13:39:58 +02:00
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//
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2019-05-14 14:39:35 +02:00
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void MmInitPaging(void)
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{
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2019-05-15 19:11:47 +02:00
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extern MemoryMap_t memoryMap;
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2019-05-16 23:56:23 +02:00
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ulong phRamSize = memoryMap.freeRamSize + memoryMap.nonfreeRamSize;
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2019-05-15 21:02:16 +02:00
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2019-05-15 15:55:57 +02:00
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memzero((void *)&MmPML4[0], sizeof(MmPML4));
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memzero((void *)&MmPDP[0], sizeof(MmPDP));
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memzero((void *)&MmPD[0], sizeof(MmPD));
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memzero((void *)&MmPT[0], sizeof(MmPT));
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2019-05-15 02:26:55 +02:00
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2019-05-16 23:56:23 +02:00
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for (volatile ulong i = 0; i < 512 * NB_4K; i++) {
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2019-05-15 15:55:57 +02:00
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// STACK GUARD PAGE
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2019-05-18 12:58:54 +02:00
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if ((ulong)(i*KPAGESIZE) == (ulong)BtLoaderInfo.stackEndAddr) {
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MmPT[i] = ((ulong)(i*KPAGESIZE));
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2019-05-22 08:11:50 +02:00
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MmStackGuards[0] = ((ulong)(i*KPAGESIZE));
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2019-05-15 15:55:57 +02:00
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continue;
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}
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2019-05-15 19:11:47 +02:00
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// ENOMEM like
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2019-05-18 12:58:54 +02:00
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if ((ulong)(i*KPAGESIZE) > (ulong)phRamSize) {
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2019-05-16 23:56:23 +02:00
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break;
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2019-05-15 15:55:57 +02:00
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}
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// STACK GARD PAGE
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2019-05-18 12:58:54 +02:00
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if ((ulong)(i*KPAGESIZE) == (ulong)BtLoaderInfo.kernelEndAddr) {
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MmPT[i] = ((ulong)(i*KPAGESIZE));
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2019-05-22 08:11:50 +02:00
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MmStackGuards[1] = ((ulong)(i*KPAGESIZE));
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2019-05-15 15:55:57 +02:00
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continue;
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}
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2019-12-30 01:22:36 +01:00
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// TEXT
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if ((ulong)(i*KPAGESIZE) >= (ulong)&_text && (ulong)(i*KPAGESIZE) <= (ulong)&_text_end) {
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MmPT[i] = ((ulong)(i*KPAGESIZE))| MF_PRESENT;
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continue;
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}
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// RODATA
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if ((ulong)(i*KPAGESIZE) >= (ulong)&_rodata && (ulong)(i*KPAGESIZE) <= (ulong)&_rodata_end) {
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2020-01-05 22:12:50 +01:00
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MmPT[i] = ((ulong)(i*KPAGESIZE)) | MF_PRESENT | MF_WRITETHR;
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2019-12-30 01:22:36 +01:00
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continue;
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}
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// DATA
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if ((ulong)(i*KPAGESIZE) >= (ulong)&_data && (ulong)(i*KPAGESIZE) <= (ulong)&_data_end) {
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2020-01-05 22:12:50 +01:00
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MmPT[i] = ((ulong)(i*KPAGESIZE)) | MF_PRESENT | MF_WRITETHR | MF_READWRITE;
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2019-12-30 01:22:36 +01:00
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continue;
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}
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2020-01-05 22:12:50 +01:00
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MmPT[i] = ((ulong)(i*KPAGESIZE)) | MF_PRESENT | MF_WRITETHR | MF_READWRITE;
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2019-05-15 11:15:21 +02:00
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}
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2019-05-16 23:56:23 +02:00
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for (volatile ulong i = 0; i < NB_4K; i++) {
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2019-05-15 15:55:57 +02:00
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MmPD[i] = (ulong)(&MmPT[i*512])| MF_PRESENT | MF_READWRITE;
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2019-05-15 11:15:21 +02:00
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}
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2019-05-16 23:56:23 +02:00
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for (volatile ulong i = NB_4K; i < 512 * RAM_MAX; i++) {
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2019-05-15 19:11:47 +02:00
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// ENOMEM like
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2019-05-18 12:58:54 +02:00
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if ((ulong)(i* UPAGESIZE) > (ulong)phRamSize) {
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2019-05-16 23:56:23 +02:00
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break;
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2019-05-15 19:11:47 +02:00
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}
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2019-05-16 23:56:23 +02:00
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MmPD[i] = 0;
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2019-05-18 12:58:54 +02:00
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MmPD[i] = ((ulong)(i* UPAGESIZE)) | MF_PRESENT | MF_READWRITE | MF_HUGE;
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2019-05-14 14:39:35 +02:00
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}
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2019-05-16 23:56:23 +02:00
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for (volatile int i = 0; i < RAM_MAX; i++) {
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2019-05-15 15:55:57 +02:00
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MmPDP[i] = (ulong)(&MmPD[i*512])| MF_PRESENT | MF_READWRITE;
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2019-05-15 02:26:55 +02:00
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}
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2019-05-15 15:55:57 +02:00
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MmPML4[0] = (ulong)(&MmPDP[0])| MF_PRESENT | MF_READWRITE;
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2019-05-14 14:39:35 +02:00
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2019-05-16 23:56:23 +02:00
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MmLoadPML4((void *)MmPML4);
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2020-01-05 22:12:50 +01:00
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MmEnableWriteProtect();
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DebugLog("\tPage RO from %p to %p\n", (ulong)&_text, (ulong)&_text_end);
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DebugLog("\tPage RO from %p to %p\n", (ulong)&_rodata, (ulong)&_rodata_end);
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2019-05-22 23:32:44 +02:00
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//DebugLog("\tPaging tables initialized at %p, %p\n", &MmPD, &MmPT);
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//DebugLog("\tStack Guards at %p, %p\n", MmStackGuards[0], MmStackGuards[1]);
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2019-05-18 13:39:58 +02:00
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}
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2019-05-22 08:11:50 +02:00
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// Returns the rank of the Stack Guards
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void *MmGetStackGuards(char rank)
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{
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return (void *)MmStackGuards[(int)rank];
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}
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// Returns an address corresponding to the PT rank
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void *MmTranslateKPageToAddr(void *rank)
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{
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return (void *)MmPT[(ulong)rank];
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}
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2019-05-18 13:39:58 +02:00
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//
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// Page fault handler
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//
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static void PagingHandler(ISRFrame_t *regs)
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{
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2019-05-22 08:35:58 +02:00
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ulong StackGuardOne = (ulong)MmGetStackGuards(0);
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if (regs->cr2 >= StackGuardOne && (regs->rsp + 4*KB >= regs->cr2)) {
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bprintf(BStdOut,
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"\n\n%CPANIC\n[ISR 0x8] Irrecoverable Kernel Stack Underflow\n\n"
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" Double Fault Error code : %#x (%b)\n"
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" Stack Guard bypassed : %#x",
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VGA_COLOR_LIGHT_RED,
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regs->ErrorCode,
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regs->ErrorCode,
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StackGuardOne
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);
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} else {
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2019-11-16 22:41:46 +01:00
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//XXX page fault
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2019-05-22 08:35:58 +02:00
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bprintf(BStdOut, "\n\n%CPANIC\n[ISR 0x%x] Irrecoverable Kernel Page Fault at %p\n\n"
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2019-05-19 01:33:16 +02:00
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" Error code : 0x%x (%b)",
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2019-05-18 20:31:02 +02:00
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2019-05-19 00:07:01 +02:00
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VGA_COLOR_LIGHT_RED,
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2019-05-18 13:39:58 +02:00
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regs->intNo,
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2019-05-18 20:31:02 +02:00
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regs->cr2,
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2019-05-18 13:39:58 +02:00
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regs->ErrorCode,
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2019-05-19 01:33:16 +02:00
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regs->ErrorCode
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2019-05-18 13:39:58 +02:00
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);
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2019-05-22 08:35:58 +02:00
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}
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2019-05-19 00:07:01 +02:00
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2019-05-19 01:33:16 +02:00
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KeBrkDumpRegisters(regs);
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2019-05-19 00:07:01 +02:00
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BStdOut->flusher(BStdOut);
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KeHaltCPU();
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2019-05-18 13:39:58 +02:00
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}
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void MmActivatePageHandler(void)
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{
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KeRegisterISR(PagingHandler, 0xe);
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2019-11-16 22:41:46 +01:00
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DebugLog("\tPaging activated\n");
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2019-05-15 02:26:55 +02:00
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}
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