os-k/kaleid/kernel/ke/idt.c

//----------------------------------------------------------------------------//
//                           GNU GPL OS/K                                     //
//                                                                            //
//  Desc:  Interrupt related functions                                        //
//                                                                            //
//                                                                            //
//  Copyright © 2018-2019 The OS/K Team                                       //
//                                                                            //
//  This file is part of OS/K.                                                //
//                                                                            //
//  OS/K is free software: you can redistribute it and/or modify              //
//  it under the terms of the GNU General Public License as published by      //
//  the Free Software Foundation, either version 3 of the License, or         //
//  any later version.                                                        //
//                                                                            //
//  OS/K is distributed in the hope that it will be useful,                   //
//  but WITHOUT ANY WARRANTY//without even the implied warranty of            //
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             //
//  GNU General Public License for more details.                              //
//                                                                            //
//  You should have received a copy of the GNU General Public License         //
//  along with OS/K.  If not, see <https://www.gnu.org/licenses/>.            //
//----------------------------------------------------------------------------//

#include <lib/buf.h>
#include <init/boot.h>
#include <ke/idt.h>

IdtEntry_t idt[256] = { 0 };
IdtPtr_t _KeIdtPtr;

static ISRList_t isrList = { 0 };

static char *ExceptionsChar[32] = {
    "Divide Error Fault",
    "Debug Exception Trap",
    "Non-maskable Interrupt",
    "Breakpoint Trap",
    "Overflow Trap",
    "Bound Range Exceeded Fault",
    "Invalid Opcode Fault",
    "Device Not Available or No Math Coprocessor Fault",
    "Double Fault Abort",
    "Coprocessor Segment Overrun Fault (Legacy)",
    "Invalid TSS Fault",
    "Segment Not Present Fault",
    "Stack Segment fault",
    "General Protection Fault",
    "Page Fault",
    "Intel Reserved",
    "x87 FPU Floating Point or Math Fault",
    "Alignment Check Fault",
    "Machine Check Abort",
    "SIMD Floating Point Fault",
    "Virtualization Exception Fault",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Intel Reserved",
    "Security Exception",
    "Intel Reserved"
};

static void EnablePIC(void);
static void EarlyExceptionHandler(ISRFrame_t *regs);

#define interrupt(n) asm volatile ("int %0" : : "N" (n) : "cc", "memory")

//
// Registers an isr with his IRQ to handle driver interrupts
//
error_t KeRegisterISR(void (*isr)(ISRFrame_t *regs), uchar isrNo)
{
    uchar n = isrList.n;
    int OverWriting = 0;

    assert(idt[0].flags!=0); // IDT initialized

    if (n == 0) goto settingUp;

    for (int i = 0; i < n; i++) {
        if (isrNo == isrList.entry[i].isrNo) {
            n = i;
            OverWriting++;
            break;
        }
    }

    if ((n == 255))             // IRQs not filled
        return ENOMEM;

settingUp:
    isrList.entry[n].isr = isr;
    isrList.entry[n].isrNo = isrNo;
    if (!OverWriting) isrList.n++;

    return EOK;
}

//
// Installs the IDT in order to activate the interrupts handling
//
void KeSetupIDT(void)
{
    // XXX detect the APIC with cpuid !
    EnablePIC();

    ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;

    // Set IDT ptr
    _KeIdtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
    _KeIdtPtr.base = &idt;

    // Set IDT Exception Gates
    KeSetIDTGate(0x00, (ulong)isr0, codeSeg, 0x8E);
    KeSetIDTGate(0x01, (ulong)isr1, codeSeg, 0x8E);
    KeSetIDTGate(0x02, (ulong)isr2, codeSeg, 0x8E);
    KeSetIDTGate(0x03, (ulong)isr3, codeSeg, 0x8E);
    KeSetIDTGate(0x04, (ulong)isr4, codeSeg, 0x8E);
    KeSetIDTGate(0x05, (ulong)isr5, codeSeg, 0x8E);
    KeSetIDTGate(0x06, (ulong)isr6, codeSeg, 0x8E);
    KeSetIDTGate(0x07, (ulong)isr7, codeSeg, 0x8E);
    KeSetIDTGate(0x08, (ulong)isr8, codeSeg, 0x8E);
    KeSetIDTGate(0x09, (ulong)isr9, codeSeg, 0x8E);
    KeSetIDTGate(0x0A, (ulong)isr10, codeSeg, 0x8E);
    KeSetIDTGate(0x0B, (ulong)isr11, codeSeg, 0x8E);
    KeSetIDTGate(0x0C, (ulong)isr12, codeSeg, 0x8E);
    KeSetIDTGate(0x0D, (ulong)isr13, codeSeg, 0x8E);
    KeSetIDTGate(0x0E, (ulong)isr14, codeSeg, 0x8E);
    KeSetIDTGate(0x0F, (ulong)isr15, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x10, (ulong)isr16, codeSeg, 0x8E);
    KeSetIDTGate(0x11, (ulong)isr17, codeSeg, 0x8E);
    KeSetIDTGate(0x12, (ulong)isr18, codeSeg, 0x8E);
    KeSetIDTGate(0x13, (ulong)isr19, codeSeg, 0x8E);
    KeSetIDTGate(0x14, (ulong)isr20, codeSeg, 0x8E);
    KeSetIDTGate(0x15, (ulong)isr21, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x16, (ulong)isr22, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x17, (ulong)isr23, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x18, (ulong)isr24, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x19, (ulong)isr25, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x1A, (ulong)isr26, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x1B, (ulong)isr27, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x1C, (ulong)isr28, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x1D, (ulong)isr29, codeSeg, 0x8E);  // INTEL RESERVED
    KeSetIDTGate(0x1E, (ulong)isr30, codeSeg, 0x8E);
    KeSetIDTGate(0x1F, (ulong)isr31, codeSeg, 0x8E);  // INTEL RESERVED

    // Set IDT IRQs Gates
    KeSetIDTGate(0x20, (ulong)isr32, codeSeg, 0x8E);
    KeSetIDTGate(0x21, (ulong)isr33, codeSeg, 0x8E);
    KeSetIDTGate(0x22, (ulong)isr34, codeSeg, 0x8E);
    KeSetIDTGate(0x23, (ulong)isr35, codeSeg, 0x8E);
    KeSetIDTGate(0x24, (ulong)isr36, codeSeg, 0x8E);
    KeSetIDTGate(0x25, (ulong)isr37, codeSeg, 0x8E);
    KeSetIDTGate(0x26, (ulong)isr38, codeSeg, 0x8E);
    KeSetIDTGate(0x27, (ulong)isr39, codeSeg, 0x8E);
    KeSetIDTGate(0x28, (ulong)isr40, codeSeg, 0x8E);
    KeSetIDTGate(0x29, (ulong)isr41, codeSeg, 0x8E);
    KeSetIDTGate(0x2A, (ulong)isr42, codeSeg, 0x8E);
    KeSetIDTGate(0x2B, (ulong)isr43, codeSeg, 0x8E);
    KeSetIDTGate(0x2C, (ulong)isr44, codeSeg, 0x8E);
    KeSetIDTGate(0x2D, (ulong)isr45, codeSeg, 0x8E);
    KeSetIDTGate(0x2E, (ulong)isr46, codeSeg, 0x8E);
    KeSetIDTGate(0x2F, (ulong)isr47, codeSeg, 0x8E);

    //Setup Early Exception handler
    for (uchar i = 0 ; i < 0x20 ; i++) {
        KeRegisterISR(EarlyExceptionHandler, i);
    }

    // Load IDT
    KeLoadIDT();
    DebugLog("\tInterrupt table initialized\n");
}

//
// Set an interrupt gate
//
void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags)
{
    // Set Base Address
    idt[rank].baseLow = base & 0xFFFF;
    idt[rank].baseMid = (base >> 16) & 0xFFFF;
    idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;

    // Set Selector
    idt[rank].selector = selector;
    idt[rank].flags = flags;

    // Set Reserved Areas to Zero
    idt[rank].reservedIst = 0;
    idt[rank].reserved = 0;
}

//
// Enable and initializes the PIC to work correctly
//
static void EnablePIC(void)
{
    // Set ICW1 - begin init of the PIC
    IoWriteByteOnPort(0x20, 0x11);
    IoWriteByteOnPort(0xa0, 0x11);

    // Set ICW2 (IRQ base offsets)
    IoWriteByteOnPort(0x21, 0x20); //0x20 is the first free interrupt for IRQ0
    IoWriteByteOnPort(0xa1, 0x28); // PIC2 is offseted to 0x28

    // Set ICW3
    IoWriteByteOnPort(0x21, 0x4);
    IoWriteByteOnPort(0xa1, 0x2);

    // Set ICW4
    IoWriteByteOnPort(0x21, 0x1);
    IoWriteByteOnPort(0xa1, 0x1);

    // Set OCW1 (interrupt masks)
    IoWriteByteOnPort(0x21, 0xff);
    IoWriteByteOnPort(0xa1, 0xff);
}

//
// Ends the current interrupt handling
//
void KeSendEOItoPIC(uchar isr)
{
    if(isr >= 8)
        IoWriteByteOnPort(0xa0,0x20);

    IoWriteByteOnPort(0x20,0x20);
}

void KeEnableNMI(void)
{
    IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) & 0x7F);
}

void KeDisableNMI(void)
{
    IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) | 0x80);
}

//
// The main ISR handler
//
void _KeHandleISR(ISRFrame_t *regs)
{
    if ((!regs) || (!regs->rip))
        KeStartPanic("[ISR ?] Unknown ISR Exception Abort\n");

    if ((regs->intNo >= 0x15) && (regs->intNo <= 0x1D))
        return; // INTEL RESERVED

    if ((regs->intNo == 0x0F) || (regs->intNo == 0x1F))
        return; // INTEL RESERVED

    for (int i = 0; i < isrList.n; i++) {
        if (regs->intNo == isrList.entry[i].isrNo) {
            isrList.entry[i].isr(regs);
            return;
        }
    }

    bprintf(BStdOut, "[ISR 0x%x] %s\n", regs->intNo, "Unknown ISR Exception");
    BStdOut->flusher(BStdOut);
    KeSendEOItoPIC(regs->intNo);
}

//
// Early CPU Exception handler
//
static void EarlyExceptionHandler(ISRFrame_t *regs)
{
    KeStartPanic("[ISR 0x%x] Irrecoverable Kernel %s\n\n"
                     "  Error code : 0x%x (%b)\n\n"
                     "  RIP: %#016lx   CS:  %#016lx   RSP: %#016lx\n"
                     "  SS:  %#016lx   RAX: %#016lx   RBX: %#016lx\n"
                     "  RCX: %#016lx   RDX: %#016lx   RSI: %#016lx\n"
                     "  RDI: %#016lx   RBP: %#016lx   R8:  %#016lx\n"
                     "  R9:  %#016lx   R10: %#016lx   R11: %#016lx\n"
                     "  R12: %#016lx   R13: %#016lx   R14: %#016lx\n"
                     "  R15: %#016lx   CR0: %#016lx   CR2: %#016lx\n"
                     "  CR3: %#016lx   CR4: %#016lx   CR8: %#016lx\n"
                     "  RFLAGS: %#022b (%#06x)",
                     regs->intNo,
                     ExceptionsChar[regs->intNo],
                     regs->ErrorCode,
                     regs->ErrorCode,
                     regs->rip,
                     regs->cs,
                     regs->rsp,
                     regs->ss,
                     regs->regs[5],
                     regs->regs[6],
                     regs->regs[7],
                     regs->regs[8],
                     regs->regs[9],
                     regs->regs[10],
                     regs->regs[11],
                     regs->regs[12],
                     regs->regs[13],
                     regs->regs[14],
                     regs->regs[15],
                     regs->regs[16],
                     regs->regs[17],
                     regs->regs[18],
                     regs->regs[19],
                     regs->regs[0],
                     regs->regs[1],
                     regs->regs[2],
                     regs->regs[3],
                     regs->regs[4],
                     regs->rflags,
                     regs->rflags
                 );
}