From bf6e226f0aed629e0cc3f23a25e4a09972ddfa29 Mon Sep 17 00:00:00 2001 From: Adrien Bourmault Date: Mon, 17 Feb 2020 18:58:45 +0100 Subject: [PATCH 1/3] Mapping only MCFG according to it size and not maximum --- include/io/pci.h | 1 + kaleid/kernel/io/pci.c | 32 +++++++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/include/io/pci.h b/include/io/pci.h index 657304d..43c8c6a 100644 --- a/include/io/pci.h +++ b/include/io/pci.h @@ -77,6 +77,7 @@ struct PciDev_t { void IoInitPCI(); void IoPciEnumerate(); PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID); +PciDev_t *IoPciGetDeviceByClass(uchar classID, uchar subclassID); uchar IoPciReadConfigByte(PciDev_t *device, ushort offset); ushort IoPciReadConfigWord(PciDev_t *device, ushort offset); diff --git a/kaleid/kernel/io/pci.c b/kaleid/kernel/io/pci.c index 862cc6b..2a5b1e8 100644 --- a/kaleid/kernel/io/pci.c +++ b/kaleid/kernel/io/pci.c @@ -141,6 +141,34 @@ PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID) PciDev_t *pciDevicePtr = (PciDev_t *)malloc(sizeof(PciDev_t)); pciDevicePtr->vendorID = vendorID; pciDevicePtr->deviceID = deviceID; + pciDevicePtr->classID = pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS); + pciDevicePtr->subclassID = pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS); + pciDevicePtr->configAddr = pciGetConfigAddr((uchar)bus, device, function, 0); + return pciDevicePtr; + } + } + } + } + return NULL; +} + +PciDev_t *IoPciGetDeviceByClass(uchar classID, uchar subclassID) +{ + if(pciConfigBaseAddress == NULL) { + KeStartPanic("Unable to access PCI configuration : MCFG table not reachable\n"); + return NULL; + } + + for(ushort bus = 0; bus < 256; bus++) { + for(uchar device = 0; device < 32; device++) { + for(uchar function = 0; function < 8; function++) { + if(classID == pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS) + && subclassID == pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS)) { + PciDev_t *pciDevicePtr = (PciDev_t *)malloc(sizeof(PciDev_t)); + pciDevicePtr->vendorID = pciReadConfigWord((uchar)bus, device, function, PCI_REG_VENDOR); + pciDevicePtr->deviceID = pciReadConfigWord((uchar)bus, device, function, PCI_REG_DEVICE); + pciDevicePtr->classID = classID; + pciDevicePtr->subclassID = subclassID; pciDevicePtr->configAddr = pciGetConfigAddr((uchar)bus, device, function, 0); return pciDevicePtr; } @@ -160,9 +188,11 @@ void IoInitPCI() DebugLog("PCI Config Base address = 0x%p\n", pciConfigBaseAddress); // Give R/W access to the configuration space - int maxI = (256 * 32 * 8 * 4096) / KPAGESIZE; + int maxI = (MCFG_table->length) / KPAGESIZE; // More secure, for(int i=0; i < maxI; i++) { + // XXX verify that page is marked busy + MmMapPage((void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE), (void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE), PRESENT | READWRITE); From a48e9a771d06c4537b3c9770dfefbadea1d0b791 Mon Sep 17 00:00:00 2001 From: Adrien Bourmault Date: Mon, 17 Feb 2020 18:58:56 +0100 Subject: [PATCH 2/3] Mapping only MCFG according to its actual size and not maximum --- kaleid/kernel/io/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kaleid/kernel/io/pci.c b/kaleid/kernel/io/pci.c index 2a5b1e8..59ac885 100644 --- a/kaleid/kernel/io/pci.c +++ b/kaleid/kernel/io/pci.c @@ -199,4 +199,4 @@ void IoInitPCI() } IoPciEnumerate(); -} +} From 26446515b34e4eb2db39a90f7023e8dbf59c58af Mon Sep 17 00:00:00 2001 From: Adrien Bourmault Date: Mon, 17 Feb 2020 18:59:04 +0100 Subject: [PATCH 3/3] Mapping only MCFG according to its actual size and not maximum --- kaleid/kernel/io/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kaleid/kernel/io/pci.c b/kaleid/kernel/io/pci.c index 59ac885..2a5b1e8 100644 --- a/kaleid/kernel/io/pci.c +++ b/kaleid/kernel/io/pci.c @@ -199,4 +199,4 @@ void IoInitPCI() } IoPciEnumerate(); -} +}