diff --git a/include/io/pci.h b/include/io/pci.h
index 239fead..657304d 100644
--- a/include/io/pci.h
+++ b/include/io/pci.h
@@ -35,11 +35,18 @@
 //
 // Device registers offsets
 //
-#define PCI_REG_VENDOR          0
-#define PCI_REG_DEVICE          2
-#define PCI_REG_COMMAND         4
-#define PCI_REG_STATUS          6
-//..
+#define PCI_REG_VENDOR          0x00
+#define PCI_REG_DEVICE          0x02
+#define PCI_REG_COMMAND         0x04
+#define PCI_REG_STATUS          0x06
+#define PCI_REG_REVISION        0x08
+#define PCI_REG_PROGIF          0x09
+#define PCI_REG_SUBCLASS        0x0A
+#define PCI_REG_CLASS           0x0B
+#define PCI_REG_CACHE_LINE_SIZE 0x0C
+#define PCI_REG_LATENCY_TIMER   0x0D
+#define PCI_REG_HEADER_TYPE     0x0E
+#define PCI_REG_BIST            0x0F
 #define PCI_REG_BAR0            0x10
 #define PCI_REG_BAR1            0x14
 #define PCI_REG_BAR2            0x18
@@ -57,6 +64,10 @@
 struct PciDev_t {
     ushort vendorID;
     ushort deviceID;
+
+    uchar classID;
+    uchar subclassID;
+
     void* configAddr;
 };
 
diff --git a/kaleid/kernel/io/pci.c b/kaleid/kernel/io/pci.c
index c80fcbe..862cc6b 100644
--- a/kaleid/kernel/io/pci.c
+++ b/kaleid/kernel/io/pci.c
@@ -115,7 +115,9 @@ void IoPciEnumerate()
             for(uchar function = 0; function < 8; function++) {
                 ushort vendor = pciReadConfigWord((uchar)bus, device, function, PCI_REG_VENDOR);
                 if(vendor == 0xffff) continue;
-                DebugLog("PCI device vendor: %x, device: %x\n",
+                DebugLog("PCI device class: %x, subclass: %x, vendor: %x, device: %x\n",
+                         pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS),
+                         pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS),
                          vendor,
                          pciReadConfigWord((uchar)bus, device, function, PCI_REG_DEVICE)
                         );
@@ -157,8 +159,6 @@ void IoInitPCI()
     pciConfigBaseAddress = MCFG_table->pciConfigBaseAddress;
     DebugLog("PCI Config Base address = 0x%p\n", pciConfigBaseAddress);
     
-    IoPciEnumerate();
-    
     // Give R/W access to the configuration space
     int maxI = (256 * 32 * 8 * 4096) / KPAGESIZE;
     for(int i=0; i < maxI; i++)
@@ -167,4 +167,6 @@ void IoInitPCI()
                   (void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE),
                   PRESENT | READWRITE);
     }
+
+    IoPciEnumerate();
 }