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Mapping only MCFG according to it size and not maximum

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This commit is contained in:
Adrien Bourmault 2020-02-17 18:58:45 +01:00
parent 41560b133d
commit bf6e226f0a
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GPG Key ID: AFEE5788AEE3F4EC
2 changed files with 32 additions and 1 deletions
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1
include/io/pci.h
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@ -77,6 +77,7 @@ struct PciDev_t {
void IoInitPCI();
void IoPciEnumerate();
PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID);
PciDev_t *IoPciGetDeviceByClass(uchar classID, uchar subclassID);
uchar IoPciReadConfigByte(PciDev_t *device, ushort offset);
ushort IoPciReadConfigWord(PciDev_t *device, ushort offset);

32
kaleid/kernel/io/pci.c
View File

@ -141,6 +141,34 @@ PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID)
PciDev_t *pciDevicePtr = (PciDev_t *)malloc(sizeof(PciDev_t));
pciDevicePtr->vendorID = vendorID;
pciDevicePtr->deviceID = deviceID;
pciDevicePtr->classID = pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS);
pciDevicePtr->subclassID = pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS);
pciDevicePtr->configAddr = pciGetConfigAddr((uchar)bus, device, function, 0);
return pciDevicePtr;
}
}
}
}
return NULL;
}
PciDev_t *IoPciGetDeviceByClass(uchar classID, uchar subclassID)
{
if(pciConfigBaseAddress == NULL) {
KeStartPanic("Unable to access PCI configuration : MCFG table not reachable\n");
return NULL;
}
for(ushort bus = 0; bus < 256; bus++) {
for(uchar device = 0; device < 32; device++) {
for(uchar function = 0; function < 8; function++) {
if(classID == pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS)
&& subclassID == pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS)) {
PciDev_t *pciDevicePtr = (PciDev_t *)malloc(sizeof(PciDev_t));
pciDevicePtr->vendorID = pciReadConfigWord((uchar)bus, device, function, PCI_REG_VENDOR);
pciDevicePtr->deviceID = pciReadConfigWord((uchar)bus, device, function, PCI_REG_DEVICE);
pciDevicePtr->classID = classID;
pciDevicePtr->subclassID = subclassID;
pciDevicePtr->configAddr = pciGetConfigAddr((uchar)bus, device, function, 0);
return pciDevicePtr;
}
@ -160,9 +188,11 @@ void IoInitPCI()
DebugLog("PCI Config Base address = 0x%p\n", pciConfigBaseAddress);
// Give R/W access to the configuration space
int maxI = (256 * 32 * 8 * 4096) / KPAGESIZE;
int maxI = (MCFG_table->length) / KPAGESIZE; // More secure,
for(int i=0; i < maxI; i++)
{
// XXX verify that page is marked busy
MmMapPage((void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE),
(void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE),
PRESENT | READWRITE);