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RTL8139 initialization

This commit is contained in:
Antoine Cure 2020-02-13 00:01:53 +01:00
parent 51fec57976
commit d76190d023
No known key found for this signature in database
GPG Key ID: DCA412F83BD81F24
2 changed files with 57 additions and 2 deletions

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@ -36,10 +36,21 @@
#define RTL8139_VENDOR_ID 0x10EC #define RTL8139_VENDOR_ID 0x10EC
#define RTL8139_DEVICE_ID 0x8139 #define RTL8139_DEVICE_ID 0x8139
// Registers
#define RTL8139_REG_CMD 0x37
#define RTL8139_REG_IMR 0x3C
#define RTL8139_REG_ISR 0x3E
#define RTL8139_REG_CONFIG1 0x52
// Config bits
#define RTL8139_BIT_ROK 0x1 // bit 0 of IMR or ISR
#define RTL8139_BIT_TOK 0x4 // bit 2 of IMR or ISR
#define RTL8139_BIT_CMD_RST 0x10 // bit 4 of CMD
//----------------------------------------------------------------------------// //----------------------------------------------------------------------------//
void initRTL8139(); void initRTL8139();
void rtl8139ISR(ISRFrame_t *regs);
#endif #endif

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@ -25,14 +25,58 @@
#include <drivers/rtl8139.h> #include <drivers/rtl8139.h>
#include <io/pci.h> #include <io/pci.h>
#include <ke/idt.h>
ushort ioBase = 0;
void rtl8139ISR(ISRFrame_t *regs)
{
ushort status = IoReadWordFromPort(ioBase + RTL8139_REG_ISR);
if(status & RTL8139_BIT_TOK) {
KernLog("Send packet !!!\n");
}
if (status & RTL8139_BIT_ROK) {
KernLog("Receive packet !!!\n");
}
}
void initRTL8139() void initRTL8139()
{ {
pciDev_t *rtl8139_pciDev = IoPciGetDevice(RTL8139_VENDOR_ID, RTL8139_DEVICE_ID); PciDev_t *rtl8139_pciDev = IoPciGetDevice(RTL8139_VENDOR_ID, RTL8139_DEVICE_ID);
if(rtl8139_pciDev != NULL) if(rtl8139_pciDev != NULL)
{ {
DebugLog("Network card RTL8139 found ! PCI config addr = %p\n", DebugLog("Network card RTL8139 found ! PCI config addr = %p\n",
rtl8139_pciDev->configAddr); rtl8139_pciDev->configAddr);
// Enable PCI bus mastering
ushort pciCommandReg = IoPciReadConfigWord(rtl8139_pciDev, PCI_REG_COMMAND);
pciCommandReg |= 4;
IoPciWriteConfigWord(rtl8139_pciDev, PCI_REG_COMMAND, pciCommandReg);
// Get I/O base address
ioBase = IoPciReadConfigDWord(rtl8139_pciDev, PCI_REG_BAR0) & (~0x3);
// Turn the card ON
IoWriteByteOnPort(ioBase + RTL8139_REG_CONFIG1, 0x0);
// Software reset
IoWriteByteOnPort(ioBase + RTL8139_REG_CMD, RTL8139_BIT_CMD_RST);
while((IoReadByteFromPort(ioBase + RTL8139_REG_CMD) & RTL8139_BIT_CMD_RST) != 0)
{}
// ... Receive buffer ...
// Set the TOK and ROK bits high of Interrupt Mask Register (IMR)
IoWriteWordOnPort(ioBase + RTL8139_REG_IMR, RTL8139_BIT_ROK | RTL8139_BIT_TOK);
// Interrupts
uchar irqNum = IoPciReadConfigByte(rtl8139_pciDev, PCI_REG_INTERRUPT_LINE);
if(!KeRegisterISR(&rtl8139ISR, irqNum)) {
//DebugLog("RTL8139 irq num: %u\n", irqNum);
}
} }
} }