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misc
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7dc39cf628
commit
da4c91d3c5
@ -125,9 +125,7 @@ void IoEnableKeyb(void)
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ulong flags = KePauseIRQs();
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KeRegisterISR(KeybHandler, 0x21);
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char readedInterruptConfig = IoReadByteFromPort(0x21);
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IoWriteByteOnPort(0x21, 0xFD & readedInterruptConfig);
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KeUnmaskIRQ(0x1);
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KeRestoreIRQs(flags);
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KeEnableNMI();
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@ -102,6 +102,7 @@ settingUp:
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isrList.entry[n].isrNo = isrNo;
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if (!OverWriting) isrList.n++;
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DebugLog("Interrupt %d registered to function %p\n", isrNo, isr);
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return EOK;
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}
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@ -260,6 +261,7 @@ void KeMaskIRQ(uchar isr)
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value = IoReadByteFromPort(port) | (1 << isr);
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IoWriteByteOnPort(port, value);
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DebugLog("ISR masked : %d\n", isr);
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}
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void KeUnmaskIRQ(uchar isr)
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@ -276,16 +278,19 @@ void KeUnmaskIRQ(uchar isr)
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value = IoReadByteFromPort(port) & ~(1 << isr);
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IoWriteByteOnPort(port, value);
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DebugLog("ISR unmasked : %d\n", isr);
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}
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void KeEnableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) & 0x7F);
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DebugLog("NMI Interrupts enabled\n");
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}
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void KeDisableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) | 0x80);
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DebugLog("NMI Interrupts disabled\n");
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}
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//
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@ -70,32 +70,32 @@ void MmInitGdt(void)
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memmove(&gdt[2], &tssDesc, sizeof(TssDescriptor_t));
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/* DebugLog("TSS\n" */
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/* "gdt[0] %#x\n" */
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/* "gdt[2] %#x\n" */
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/* "access : %#x\n" */
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/* "flags : %#x\n" */
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/* "lowBase : %#x\n" */
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/* "middleBase : %#x\n" */
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/* "highBase : %#x\n" */
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/* "veryHighBase: %#x\n" */
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/* "lowLimit : %#x\n" */
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/* "ist : %#x\n" */
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/* "iomap_base : %#x\n" */
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/* "offset : %#x\n", */
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/* &gdt[0], */
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/* &gdt[2], */
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/* tssDesc.access, */
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/* tssDesc.flags, */
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/* tssDesc.lowBase, */
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/* tssDesc.middleBase, */
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/* tssDesc.highBase, */
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/* tssDesc.veryHighBase, */
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/* tssDesc.lowLimit, */
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/* tss.ist1, */
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/* tss.iomap_base, */
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/* tssOffset */
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/* ); */
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DebugLog("TSS setting up :\n"
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"gdt[0] %#x\n"
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"gdt[2] %#x\n"
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"access : %#x\n"
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"flags : %#x\n"
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"lowBase : %#x\n"
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"middleBase : %#x\n"
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"highBase : %#x\n"
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"veryHighBase: %#x\n"
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"lowLimit : %#x\n"
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"ist : %#x\n"
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"iomap_base : %#x\n"
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"offset : %#x\n",
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&gdt[0],
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&gdt[2],
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tssDesc.access,
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tssDesc.flags,
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tssDesc.lowBase,
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tssDesc.middleBase,
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tssDesc.highBase,
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tssDesc.veryHighBase,
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tssDesc.lowLimit,
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tss.ist1,
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tss.iomap_base,
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tssOffset
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);
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MmLoadGdt(&gdtPtr, tssOffset);
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}
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@ -58,6 +58,8 @@ void MmInitHeap(void)
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if ((ulong)_heap_start == _heap_max)
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KeStartPanic("The heap failed to initialize ! (Not enough memory)");
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DebugLog("Heap initialized from %p to %p\n", _heap_start, _heap_max);
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}
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//
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@ -67,6 +67,8 @@ static error_t InitMemoryMap(void)
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mapEnd = (multiboot_memory_map_t*)
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((ulong)currentEntry + (ulong)BtMemoryInfo.mapLength);
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DebugLog("Initiliazing memory map...\n");
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// fill the map
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while (currentEntry < mapEnd) {
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@ -80,6 +82,15 @@ static error_t InitMemoryMap(void)
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memoryMap.entry[i].type = (uint)currentEntry->type;
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// Adding the size to the size (yup)
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memoryMap.length++;
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DebugLog("Zone: %lp type %d with length: %4luMB+%4luKB+%4luB\n",
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memoryMap.entry[i].addr,
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memoryMap.entry[i].type,
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_ADDR_TO_MB(memoryMap.entry[i].length),
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_ADDR_TO_KB(memoryMap.entry[i].length),
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_ADDR_TO_B(memoryMap.entry[i].length)
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);
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// moving up !
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currentEntry = (multiboot_memory_map_t*) ((ulong)currentEntry +
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currentEntry->size + sizeof(currentEntry->size));
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@ -492,5 +492,5 @@ static void PagingHandler(ISRFrame_t *regs)
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void MmActivatePageHandler(void)
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{
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KeRegisterISR(PagingHandler, 0xe);
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//DebugLog("\tPage handler activated\n");
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DebugLog("Page handler activated\n");
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}
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@ -216,6 +216,10 @@ ulong MmAllocPageFrame(size_t size, bool contiguous)
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NSuccessfulAlloc++;
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DebugLog("Allocate page frame id %d, size %d MB, contiguousness %d\n",
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id, size / MB, contiguous
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);
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return id;
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}
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@ -237,8 +241,12 @@ void MmFreePageFrame(ulong id)
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}
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}
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if (success)
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if (success) {
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NSuccessfulFree++;
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DebugLog("Free page frame id %d\n",
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id
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);
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}
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}
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//
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