11 Commits

Author	SHA1	Message	Date
Adrien Bourmault	d3db4efba4	Syscall vector operational (for kernel mode)	2021-02-26 19:10:25 +01:00
Adrien Bourmault	b270c2608c	Don't need more ISR than IRQ lines + syscall vector	2021-02-26 17:03:39 +01:00
Adrien Bourmault	e00ce40c6e	int 0x80 is triggered (but nothing printed though) ... * Better gdb options (hbreak) * 255 isr can now be registered * EarlyExceptionHandler is static	2021-02-26 13:18:20 +01:00
Adrien Bourmault	65694e4b5e	Happy new year ! (a bit late)	2021-02-18 19:54:35 +01:00
Adrien Bourmault	33a614d8e2	Legal update	2020-09-27 17:33:48 +02:00
Adrien Bourmault	849a0393a7	Update legals : repository copyright dates	2020-02-06 14:25:31 +01:00
Adrien Bourmault	737bea025f	Minor corrections	2020-01-08 00:28:10 +01:00
Adrien Bourmault	5829d7a353	New TSS IST used by all ISRs	2020-01-05 20:13:53 +01:00
Adrien Bourmault	e5f2aaed04	Better dump	2019-05-18 20:31:02 +02:00
Adrien Bourmault	1213055aff	Pushing more registers	2019-05-18 00:03:35 +02:00
Julian Barathieu	78622a134d	cpu => ke	2019-05-14 13:17:24 +02:00