//----------------------------------------------------------------------------//
//                           GNU GPL OS/K                                     //
//                                                                            //
//  Desc:      PCI driver                                                     //
//                                                                            //
//                                                                            //
//  Copyright © 2018-2020 The OS/K Team                                       //
//                                                                            //
//  This file is part of OS/K.                                                //
//                                                                            //
//  OS/K is free software: you can redistribute it and/or modify              //
//  it under the terms of the GNU General Public License as published by      //
//  the Free Software Foundation, either version 3 of the License, or         //
//  any later version.                                                        //
//                                                                            //
//  OS/K is distributed in the hope that it will be useful,                   //
//  but WITHOUT ANY WARRANTY//without even the implied warranty of            //
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             //
//  GNU General Public License for more details.                              //
//                                                                            //
//  You should have received a copy of the GNU General Public License         //
//  along with OS/K.  If not, see <https://www.gnu.org/licenses/>.            //
//----------------------------------------------------------------------------//


#ifndef _KERNEL_H
#include <kernel.h>
#endif



#ifndef _IO_PCI_H
#define _IO_PCI_H

//
// Device registers offsets
//
#define PCI_REG_VENDOR          0x00
#define PCI_REG_DEVICE          0x02
#define PCI_REG_COMMAND         0x04
#define PCI_REG_STATUS          0x06
#define PCI_REG_REVISION        0x08
#define PCI_REG_PROGIF          0x09
#define PCI_REG_SUBCLASS        0x0A
#define PCI_REG_CLASS           0x0B
#define PCI_REG_CACHE_LINE_SIZE 0x0C
#define PCI_REG_LATENCY_TIMER   0x0D
#define PCI_REG_HEADER_TYPE     0x0E
#define PCI_REG_BIST            0x0F
#define PCI_REG_BAR0            0x10
#define PCI_REG_BAR1            0x14
#define PCI_REG_BAR2            0x18
#define PCI_REG_BAR3            0x1C
#define PCI_REG_BAR4            0x20
#define PCI_REG_BAR5            0x24
//..
#define PCI_REG_INTERRUPT_LINE  0x3C
//..


//----------------------------------------------------------------------------//


struct PciDev_t {
    ushort vendorID;
    ushort deviceID;

    uchar classID;
    uchar subclassID;

    void* configAddr;
};


//----------------------------------------------------------------------------//

void IoInitPCI();
void IoPciEnumerate();
PciDev_t *IoPciGetDevice(ushort vendorID, ushort deviceID);

uchar IoPciReadConfigByte(PciDev_t *device, ushort offset);
ushort IoPciReadConfigWord(PciDev_t *device, ushort offset);
uint IoPciReadConfigDWord(PciDev_t *device, ushort offset);


void IoPciWriteConfigByte(PciDev_t *device, ushort offset, uchar data);
void IoPciWriteConfigWord(PciDev_t *device, ushort offset, ushort data);
void IoPciWriteConfigDWord(PciDev_t *device, ushort offset, uint data);


#endif