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412 lines
13 KiB
C
412 lines
13 KiB
C
//----------------------------------------------------------------------------//
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// GNU GPL OS/K //
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// //
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// Desc: Interrupt related functions //
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// //
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// //
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// Copyright © 2018-2019 The OS/K Team //
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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//----------------------------------------------------------------------------//
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#include <lib/buf.h>
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#include <init/boot.h>
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#include <ke/idt.h>
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#include <io/vga.h>
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#include <mm/mm.h>
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#include <io/spkr.h>
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IdtEntry_t idt[256] = { 0 };
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IdtPtr_t _KeIdtPtr;
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bool KeIdtIsInitialized = 0;
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static ISRList_t isrList = { 0 };
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static char *ExceptionsChar[32] = {
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"Divide Error Fault",
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"Debug Exception Trap",
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"Non-maskable Interrupt",
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"Breakpoint Trap",
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"Overflow Trap",
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"Bound Range Exceeded Fault",
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"Invalid Opcode Fault",
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"Device Not Available or No Math Coprocessor Fault",
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"Double Fault Abort",
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"Coprocessor Segment Overrun Fault (Legacy)",
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"Invalid TSS Fault",
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"Segment Not Present Fault",
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"Stack Segment fault",
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"General Protection Fault",
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"Page Fault",
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"Intel Reserved",
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"x87 FPU Floating Point or Math Fault",
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"Alignment Check Fault",
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"Machine Check Abort",
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"SIMD Floating Point Fault",
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"Virtualization Exception Fault",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Security Exception",
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"Intel Reserved"
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};
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static void EnablePIC(void);
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static void EarlyExceptionHandler(ISRFrame_t *regs);
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static void DoubleFaultHandler(ISRFrame_t *regs);
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//
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// Registers an isr with his IRQ to handle driver interrupts
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//
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error_t KeRegisterISR(void (*isr)(ISRFrame_t *regs), uchar isrNo)
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{
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uchar n = isrList.n;
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int OverWriting = 0;
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assert(KeIdtIsInitialized); // IDT initialized
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if (n == 0) goto settingUp;
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for (int i = 0; i < n; i++) {
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if (isrNo == isrList.entry[i].isrNo) {
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n = i;
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OverWriting++;
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break;
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}
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}
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if ((n == 255)) // IRQs not filled
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return ENOMEM;
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settingUp:
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isrList.entry[n].isr = isr;
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isrList.entry[n].isrNo = isrNo;
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if (!OverWriting) isrList.n++;
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return EOK;
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}
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//
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// Installs the IDT in order to activate the interrupts handling
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//
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void KeSetupIDT(void)
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{
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// XXX detect the APIC with cpuid and, perhaps, use it !
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EnablePIC();
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ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
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// Set IDT ptr
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_KeIdtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
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_KeIdtPtr.base = &idt;
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// Set IDT Exception Gates
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KeSetIDTGate(0x00, (ulong)isr0, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x01, (ulong)isr1, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x02, (ulong)isr2, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x03, (ulong)isr3, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x04, (ulong)isr4, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x05, (ulong)isr5, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x06, (ulong)isr6, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x07, (ulong)isr7, codeSeg, 0x8E, 2); // XXX device not available, useful for FPU save/restore when multitasking
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KeSetIDTGate(0x08, (ulong)isr8, codeSeg, 0x8E, 1); // DOUBLE FAULT
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KeSetIDTGate(0x09, (ulong)isr9, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x0A, (ulong)isr10, codeSeg, 0x8E, 0); // INVALID TSS
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KeSetIDTGate(0x0B, (ulong)isr11, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x0C, (ulong)isr12, codeSeg, 0x8E, 1); // STACK SEGMENT FAULT
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KeSetIDTGate(0x0D, (ulong)isr13, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x0E, (ulong)isr14, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x0F, (ulong)isr15, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x10, (ulong)isr16, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x11, (ulong)isr17, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x12, (ulong)isr18, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x13, (ulong)isr19, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x14, (ulong)isr20, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x15, (ulong)isr21, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x16, (ulong)isr22, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x17, (ulong)isr23, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x18, (ulong)isr24, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x19, (ulong)isr25, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x1A, (ulong)isr26, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x1B, (ulong)isr27, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x1C, (ulong)isr28, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x1D, (ulong)isr29, codeSeg, 0x8E, 2); // INTEL RESERVED
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KeSetIDTGate(0x1E, (ulong)isr30, codeSeg, 0x8E, 2);
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KeSetIDTGate(0x1F, (ulong)isr31, codeSeg, 0x8E, 2); // INTEL RESERVED
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// Set IDT IRQs Gates
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KeSetIDTGate(0x20, (ulong)isr32, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x21, (ulong)isr33, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x22, (ulong)isr34, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x23, (ulong)isr35, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x24, (ulong)isr36, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x25, (ulong)isr37, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x26, (ulong)isr38, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x27, (ulong)isr39, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x28, (ulong)isr40, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x29, (ulong)isr41, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2A, (ulong)isr42, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2B, (ulong)isr43, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2C, (ulong)isr44, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2D, (ulong)isr45, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2E, (ulong)isr46, codeSeg, 0x8E, 3);
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KeSetIDTGate(0x2F, (ulong)isr47, codeSeg, 0x8E, 3);
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KeIdtIsInitialized++;
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//Setup Early Exception handler
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for (uchar i = 0 ; i < 0x20 ; i++) {
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KeRegisterISR(EarlyExceptionHandler, i);
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}
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KeRegisterISR(KeBrkDumpRegisters, 0x3);
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KeRegisterISR(DoubleFaultHandler, 0x8);
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// Load IDT
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KeLoadIDT();
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//DebugLog("\tInterrupt table initialized at %p\n", _KeIdtPtr.base);
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KernLog("\tInterrupts activated\n");
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}
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//
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// Set an interrupt gate
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//
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void KeSetIDTGate(uchar rank, ulong base, ushort selector, uchar flags, uchar ist)
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{
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// Set Base Address
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idt[rank].baseLow = base & 0xFFFF;
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idt[rank].baseMid = (base >> 16) & 0xFFFF;
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idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;
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// Set Selector
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idt[rank].selector = selector;
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idt[rank].flags = flags;
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// Set Reserved Areas to Zero
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idt[rank].ist = ist;
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idt[rank].reserved = 0;
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}
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//
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// Enable and initializes the PIC to work correctly
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//
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static void EnablePIC(void)
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{
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// Set ICW1 - begin init of the PIC
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IoWriteByteOnPort(0x20, 0x11);
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IoWriteByteOnPort(0xa0, 0x11);
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// Set ICW2 (IRQ base offsets)
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IoWriteByteOnPort(0x21, 0x20); //0x20 is the first free interrupt for IRQ0
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IoWriteByteOnPort(0xa1, 0x28); // PIC2 is offseted to 0x28
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// Set ICW3
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IoWriteByteOnPort(0x21, 0x4);
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IoWriteByteOnPort(0xa1, 0x2);
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// Set ICW4
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IoWriteByteOnPort(0x21, 0x1);
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IoWriteByteOnPort(0xa1, 0x1);
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// Set OCW1 (interrupt masks)
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IoWriteByteOnPort(0x21, 0xff);
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IoWriteByteOnPort(0xa1, 0xff);
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char readIrqs = IoReadByteFromPort(0x21);
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IoWriteByteOnPort(0x21, 0xFB & readIrqs); // Enables IRQ forwarding from PIC2 to PIC 1
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}
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//
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// Ends the current interrupt handling
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//
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void KeSendEOItoPIC(uchar isr)
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{
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if(isr >= 8)
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IoWriteByteOnPort(0xa0,0x20);
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IoWriteByteOnPort(0x20,0x20);
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}
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void KeMaskIRQ(uchar isr)
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{
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uchar port;
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uchar value;
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if(isr < 0x8) {
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port = 0x21;
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} else {
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port = 0xA1;
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isr -= 8;
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}
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value = IoReadByteFromPort(port) | (1 << isr);
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IoWriteByteOnPort(port, value);
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}
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void KeUnmaskIRQ(uchar isr)
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{
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uchar port;
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uchar value;
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if(isr < 0x8) {
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port = 0x21;
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} else {
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port = 0xA1;
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isr -= 8;
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}
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value = IoReadByteFromPort(port) & ~(1 << isr);
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IoWriteByteOnPort(port, value);
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}
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void KeEnableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) & 0x7F);
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}
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void KeDisableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) | 0x80);
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}
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//
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// The main ISR handler
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//
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void _KeHandleISR(ISRFrame_t *regs)
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{
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/* if ((!regs) || (!regs->rip)) */
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/* KeStartPanic("[ISR ?] Unknown ISR Exception Abort\n"); */
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if ((regs->intNo >= 0x15) && (regs->intNo <= 0x1D))
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return; // INTEL RESERVED
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if ((regs->intNo == 0x0F) || (regs->intNo == 0x1F))
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return; // INTEL RESERVED
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for (int i = 0; i < isrList.n; i++) {
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if (regs->intNo == isrList.entry[i].isrNo) {
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isrList.entry[i].isr(regs);
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return;
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}
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}
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bprintf(BStdOut, "[ISR 0x%x] %s\n", regs->intNo, "Unknown ISR Exception");
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BStdOut->flusher(BStdOut);
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KeSendEOItoPIC(regs->intNo);
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}
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//
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// Early CPU Exception handler
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//
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static void EarlyExceptionHandler(ISRFrame_t *regs)
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{
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bprintf(BStdOut, "\n\n%CPANIC\n[ISR 0x%x] Irrecoverable Kernel %s\n\n"
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" Error code : 0x%x (%b)",
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VGA_COLOR_LIGHT_RED,
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regs->intNo,
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ExceptionsChar[regs->intNo],
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regs->ErrorCode,
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regs->ErrorCode
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);
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KeBrkDumpRegisters(regs);
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BStdOut->flusher(BStdOut);
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KeHaltCPU();
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}
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//
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// Double Fault handling and stack overflow detection
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//
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static void DoubleFaultHandler(ISRFrame_t *regs)
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{
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bprintf(BStdOut,
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"\n\n%CPANIC\n[ISR 0x8] Irrecoverable Kernel Double Fault Abort\n\n"
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" Error code : 0x%x (%b)",
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VGA_COLOR_LIGHT_RED,
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regs->ErrorCode,
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regs->ErrorCode
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);
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KeBrkDumpRegisters(regs);
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BStdOut->flusher(BStdOut);
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KeHaltCPU();
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}
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void KeBrkDumpRegisters(ISRFrame_t *regs)
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{
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IoDoBeepNoIdt();
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bprintf(BStdOut, "\n\n"
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"%C RIP: %#016lx RSP: %#016lx RBP: %#016lx\n\n"
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" SS: %#016lx CS: %#016lx CR0: %#016lx\n"
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" CR2: %#016lx CR3: %#016lx CR4: %#016lx\n"
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" CR8: %#016lx EFE: %#016lx \n\n"
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" RAX: %#016lx RBX: %#016lx RCX: %#016lx\n"
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" RDX: %#016lx RSI: %#016lx RDI: %#016lx\n"
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" R8: %#016lx R9: %#016lx R10: %#016lx\n"
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" R11: %#016lx R12: %#016lx R13: %#016lx\n"
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" R14: %#016lx R15: %#016lx \n\n"
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" RFLAGS: %#022b (%#06x)",
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VGA_COLOR_LIGHT_RED,
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regs->rip,
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regs->rsp,
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regs->rbp,
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regs->ss,
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regs->cs,
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regs->cr0,
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regs->cr2,
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regs->cr3,
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regs->cr4,
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regs->cr8,
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regs->efer,
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regs->rax,
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regs->rbx,
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regs->rcx,
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regs->rdx,
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regs->rsi,
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regs->rdi,
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regs->r8,
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regs->r9,
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regs->r10,
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regs->r11,
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regs->r12,
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regs->r13,
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regs->r14,
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regs->r15,
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regs->rflags,
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regs->rflags
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);
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BStdOut->flusher(BStdOut);
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}
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