mirror of
https://gitlab.os-k.eu/os-k-team/os-k.git
synced 2023-08-25 14:03:10 +02:00
129 lines
5.2 KiB
C
129 lines
5.2 KiB
C
//----------------------------------------------------------------------------//
|
|
// GNU GPL OS/K //
|
|
// //
|
|
// Desc: Interrupt related functions //
|
|
// //
|
|
// //
|
|
// Copyright © 2018-2019 The OS/K Team //
|
|
// //
|
|
// This file is part of OS/K. //
|
|
// //
|
|
// OS/K is free software: you can redistribute it and/or modify //
|
|
// it under the terms of the GNU General Public License as published by //
|
|
// the Free Software Foundation, either version 3 of the License, or //
|
|
// any later version. //
|
|
// //
|
|
// OS/K is distributed in the hope that it will be useful, //
|
|
// but WITHOUT ANY WARRANTY//without even the implied warranty of //
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
|
|
// GNU General Public License for more details. //
|
|
// //
|
|
// You should have received a copy of the GNU General Public License //
|
|
// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
|
|
//----------------------------------------------------------------------------//
|
|
|
|
#include <kernel/base.h>
|
|
#include <kernel/cpu.h>
|
|
#include <kernel/boot.h>
|
|
#include <kernel/iomisc.h>
|
|
|
|
IdtEntry_t idt[256] = { 0 };
|
|
IdtPtr_t idtPtr;
|
|
|
|
void CpuIdtSetup(void)
|
|
{
|
|
disablePIC();
|
|
|
|
ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
|
|
|
|
// Set IDT ptr
|
|
idtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
|
|
idtPtr.base = &idt;
|
|
|
|
// Set IDT gates
|
|
idtSet(0, (ulong)isr0, codeSeg, 0x8E);
|
|
idtSet(1, (ulong)isr1, codeSeg, 0x8E);
|
|
idtSet(2, (ulong)isr2, codeSeg, 0x8E);
|
|
idtSet(3, (ulong)isr3, codeSeg, 0x8E);
|
|
idtSet(4, (ulong)isr4, codeSeg, 0x8E);
|
|
idtSet(5, (ulong)isr5, codeSeg, 0x8E);
|
|
idtSet(6, (ulong)isr6, codeSeg, 0x8E);
|
|
idtSet(7, (ulong)isr7, codeSeg, 0x8E);
|
|
idtSet(8, (ulong)isr8, codeSeg, 0x8E);
|
|
idtSet(9, (ulong)isr9, codeSeg, 0x8E);
|
|
idtSet(10, (ulong)isr10, codeSeg, 0x8E);
|
|
idtSet(11, (ulong)isr11, codeSeg, 0x8E);
|
|
idtSet(12, (ulong)isr12, codeSeg, 0x8E);
|
|
idtSet(13, (ulong)isr13, codeSeg, 0x8E);
|
|
idtSet(14, (ulong)isr14, codeSeg, 0x8E);
|
|
//idtSet(15, (ulong)isr15, codeSeg, 0x8E); INTEL RESERVED
|
|
idtSet(16, (ulong)isr16, codeSeg, 0x8E);
|
|
idtSet(17, (ulong)isr17, codeSeg, 0x8E);
|
|
idtSet(18, (ulong)isr18, codeSeg, 0x8E);
|
|
idtSet(19, (ulong)isr19, codeSeg, 0x8E);
|
|
idtSet(20, (ulong)isr20, codeSeg, 0x8E);
|
|
//idtSet(21, (ulong)isr21, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(22, (ulong)isr22, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(23, (ulong)isr23, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(24, (ulong)isr24, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(25, (ulong)isr25, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(26, (ulong)isr26, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(27, (ulong)isr27, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(28, (ulong)isr28, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(29, (ulong)isr29, codeSeg, 0x8E); INTEL RESERVED
|
|
//idtSet(30, (ulong)isr30, codeSeg, 0x8E); INTEL RESERVED
|
|
|
|
// Load IDT
|
|
DebugLog("[IdtSetup] Filled \n");
|
|
idtInit();
|
|
DebugLog("[IdtSetup] Initialized !\n");
|
|
}
|
|
|
|
void idtSet(uchar rank, ulong base, ushort selector, uchar flags)
|
|
{
|
|
// Set Base Address
|
|
idt[rank].baseLow = base & 0xFFFF;
|
|
idt[rank].baseMid = (base >> 16) & 0xFFFF;
|
|
idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;
|
|
|
|
// Set Selector
|
|
idt[rank].selector = selector;
|
|
idt[rank].flags = flags;
|
|
|
|
// Set Reserved Areas to Zero
|
|
idt[rank].reservedIst = 0;
|
|
idt[rank].reserved = 0;
|
|
}
|
|
|
|
void disablePIC(void) {
|
|
// Set ICW1
|
|
IoWriteByteOnPort(0x20, 0x11);
|
|
IoWriteByteOnPort(0xa0, 0x11);
|
|
|
|
// Set ICW2 (IRQ base offsets)
|
|
IoWriteByteOnPort(0x21, 0xe0);
|
|
IoWriteByteOnPort(0xa1, 0xe8);
|
|
|
|
// Set ICW3
|
|
IoWriteByteOnPort(0x21, 4);
|
|
IoWriteByteOnPort(0xa1, 2);
|
|
|
|
// Set ICW4
|
|
IoWriteByteOnPort(0x21, 1);
|
|
IoWriteByteOnPort(0xa1, 1);
|
|
|
|
// Set OCW1 (interrupt masks)
|
|
IoWriteByteOnPort(0x21, 0xff);
|
|
IoWriteByteOnPort(0xa1, 0xff);
|
|
|
|
// ENABLING LOCAL APIC
|
|
uint *val = (void*)0xfee000f0;
|
|
*val |= (1<<8);
|
|
}
|
|
|
|
void isrHandler(Registers_t regs)
|
|
{
|
|
DebugLog("Interrupt %d !!! \n", regs.intNo);
|
|
return;
|
|
}
|