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311 lines
10 KiB
C
311 lines
10 KiB
C
//----------------------------------------------------------------------------//
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// GNU GPL OS/K //
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// //
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// Desc: Interrupt related functions //
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// //
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// //
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// Copyright © 2018-2019 The OS/K Team //
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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//----------------------------------------------------------------------------//
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#include <kernel/base.h>
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#include <kernel/idt.h>
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#include <kernel/boot.h>
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#include <kernel/iomisc.h>
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#include <extras/buf.h>
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IdtEntry_t idt[256] = { 0 };
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IdtPtr_t idtPtr;
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IRQList_t irqList = { 0 };
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char *IsrExceptions[32] = {
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"Divide Error Fault",
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"Debug Exception Trap",
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"Non-maskable Interrupt",
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"Breakpoint Trap",
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"Overflow Trap",
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"Bound Range Exceeded Fault",
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"Invalid Opcode Fault",
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"Device Not Available or No Math Coprocessor Fault",
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"Double Fault Abort",
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"Coprocessor Segment Overrun Fault (Legacy)",
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"Invalid TSS Fault",
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"Segment Not Present Fault",
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"Stack Segment fault",
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"General Protection Fault",
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"Page Fault",
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"Intel Reserved",
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"x87 FPU Floating Point or Math Fault",
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"Alignment Check Fault",
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"Machine Check Abort",
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"SIMD Floating Point Fault",
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"Virtualization Exception Fault",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Intel Reserved",
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"Security Exception",
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"Intel Reserved"
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};
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static void EnablePIC(void);
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#define interrupt(n) asm volatile ("int %0" : : "N" (n) : "cc", "memory")
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//
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// Registers an isr with his IRQ to handle driver interrupts
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//
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void IdtRegisterIrq(void (*isr)(ISRFrame_t *regs), uchar irq, uchar flags)
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{
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uchar n = irqList.n;
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KalAssert(idt[0].flags!=0); // IDT initialized
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if ((n == 224)) // IRQs not filled
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KeStartPanic("[IdtRegisterIrq] Cannot register IRQ %c function %p !",
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irq,
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isr
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);
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irqList.entry[n].isr = isr;
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irqList.entry[n].irq = irq;
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irqList.entry[n].flags = flags;
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irqList.n++;
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}
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//
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// Installs the IDT in order to activate the interrupts handling
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//
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void IdtSetup(void)
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{
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// XXX detect the APIC with cpuid !
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EnablePIC();
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ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
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// Set IDT ptr
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idtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
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idtPtr.base = &idt;
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// Set IDT Exception Gates
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IdtSetGate(0, (ulong)isr0, codeSeg, 0x8E);
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IdtSetGate(1, (ulong)isr1, codeSeg, 0x8E);
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IdtSetGate(2, (ulong)isr2, codeSeg, 0x8E);
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IdtSetGate(3, (ulong)isr3, codeSeg, 0x8E);
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IdtSetGate(4, (ulong)isr4, codeSeg, 0x8E);
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IdtSetGate(5, (ulong)isr5, codeSeg, 0x8E);
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IdtSetGate(6, (ulong)isr6, codeSeg, 0x8E);
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IdtSetGate(7, (ulong)isr7, codeSeg, 0x8E);
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IdtSetGate(8, (ulong)isr8, codeSeg, 0x8E);
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IdtSetGate(9, (ulong)isr9, codeSeg, 0x8E);
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IdtSetGate(10, (ulong)isr10, codeSeg, 0x8E);
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IdtSetGate(11, (ulong)isr11, codeSeg, 0x8E);
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IdtSetGate(12, (ulong)isr12, codeSeg, 0x8E);
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IdtSetGate(13, (ulong)isr13, codeSeg, 0x8E);
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IdtSetGate(14, (ulong)isr14, codeSeg, 0x8E);
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IdtSetGate(15, (ulong)isr15, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(16, (ulong)isr16, codeSeg, 0x8E);
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IdtSetGate(17, (ulong)isr17, codeSeg, 0x8E);
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IdtSetGate(18, (ulong)isr18, codeSeg, 0x8E);
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IdtSetGate(19, (ulong)isr19, codeSeg, 0x8E);
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IdtSetGate(20, (ulong)isr20, codeSeg, 0x8E);
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IdtSetGate(21, (ulong)isr21, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(22, (ulong)isr22, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(23, (ulong)isr23, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(24, (ulong)isr24, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(25, (ulong)isr25, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(26, (ulong)isr26, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(27, (ulong)isr27, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(28, (ulong)isr28, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(29, (ulong)isr29, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(30, (ulong)isr30, codeSeg, 0x8E); // INTEL RESERVED
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IdtSetGate(31, (ulong)isr31, codeSeg, 0x8E); // INTEL RESERVED
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// Set IDT IRQs Gates
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IdtSetGate(32, (ulong)isr32, codeSeg, 0x8E);
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IdtSetGate(33, (ulong)isr33, codeSeg, 0x8E);
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IdtSetGate(34, (ulong)isr34, codeSeg, 0x8E);
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IdtSetGate(35, (ulong)isr35, codeSeg, 0x8E);
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IdtSetGate(36, (ulong)isr36, codeSeg, 0x8E);
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IdtSetGate(37, (ulong)isr37, codeSeg, 0x8E);
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IdtSetGate(38, (ulong)isr38, codeSeg, 0x8E);
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IdtSetGate(39, (ulong)isr39, codeSeg, 0x8E);
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IdtSetGate(40, (ulong)isr40, codeSeg, 0x8E);
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IdtSetGate(41, (ulong)isr41, codeSeg, 0x8E);
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IdtSetGate(42, (ulong)isr42, codeSeg, 0x8E);
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IdtSetGate(43, (ulong)isr43, codeSeg, 0x8E);
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IdtSetGate(44, (ulong)isr44, codeSeg, 0x8E);
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IdtSetGate(45, (ulong)isr45, codeSeg, 0x8E);
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IdtSetGate(46, (ulong)isr46, codeSeg, 0x8E);
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IdtSetGate(47, (ulong)isr47, codeSeg, 0x8E);
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// Load IDT
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IdtInit();
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DebugLog("[IdtSetup] Initialized !\n");
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}
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//
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// Set an interrupt gate
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//
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void IdtSetGate(uchar rank, ulong base, ushort selector, uchar flags)
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{
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// Set Base Address
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idt[rank].baseLow = base & 0xFFFF;
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idt[rank].baseMid = (base >> 16) & 0xFFFF;
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idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;
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// Set Selector
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idt[rank].selector = selector;
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idt[rank].flags = flags;
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// Set Reserved Areas to Zero
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idt[rank].reservedIst = 0;
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idt[rank].reserved = 0;
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}
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//
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// Enable and initializes the PIC to work correctly
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//
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static void EnablePIC(void)
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{
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// Set ICW1 - begin init of the PIC
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IoWriteByteOnPort(0x20, 0x11);
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IoWriteByteOnPort(0xa0, 0x11);
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// Set ICW2 (IRQ base offsets)
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IoWriteByteOnPort(0x21, 0x20); //0x20 is the first free interrupt for IRQ0
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IoWriteByteOnPort(0xa1, 0x28); // PIC2 is offseted to 0x28
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// Set ICW3
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IoWriteByteOnPort(0x21, 0x4);
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IoWriteByteOnPort(0xa1, 0x2);
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// Set ICW4
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IoWriteByteOnPort(0x21, 0x1);
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IoWriteByteOnPort(0xa1, 0x1);
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// Set OCW1 (interrupt masks)
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IoWriteByteOnPort(0x21, 0xff);
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IoWriteByteOnPort(0xa1, 0xff);
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}
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//
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// Ends the current interrupt handling
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//
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void IoSendEOItoPIC(uchar isr)
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{
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if(isr >= 8)
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IoWriteByteOnPort(0xa0,0x20);
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IoWriteByteOnPort(0x20,0x20);
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}
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void IoEnableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) & 0x7F);
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}
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void IoDisableNMI(void)
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{
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IoWriteByteOnPort(0x70, IoReadByteFromPort(0x70) | 0x80);
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}
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//
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// The main ISR handler
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//
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void IsrHandler(ISRFrame_t *regs)
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{
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if ((!regs) || (!regs->rip))
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KeStartPanic("[ISR ?] Unknown ISR Exception Abort\n");
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if ((regs->intNo >= 21) && (regs->intNo <= 31))
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return; // INTEL RESERVED
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if (regs->intNo == 15)
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return; // INTEL RESERVED
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if (regs->intNo < 32) {
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IdtExceptionHandler(regs);
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return;
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}
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for (int i = 0; i < irqList.n; i++) {
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if (regs->intNo == irqList.entry[i].irq) {
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irqList.entry[i].isr(regs);
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return;
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}
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}
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bprintf(BStdOut, "[ISR 0x%x] %s\n", regs->intNo, "Unknown ISR Exception");
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BStdOut->flusher(BStdOut);
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IoSendEOItoPIC(regs->intNo);
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/* KeStartPanic("[ISR 0x%x] Unknown ISR Exception Abort\n" */
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/* " Error code : 0x%x\n" */
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/* " RIP:\t\t%p\n" */
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/* " CS:\t\t%p\n" */
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/* " RFLAGS:\t%022b\n" */
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/* " RSP:\t\t%p\n" */
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/* " SS:\t\t%p\n", */
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/* regs->intNo, */
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/* regs->ErrorCode, */
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/* regs->rip, */
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/* regs->cs, */
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/* regs->rflags, */
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/* regs->rsp, */
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/* regs->ss */
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/* ); */
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}
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//
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// CPU Exception handler
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//
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void IdtExceptionHandler(ISRFrame_t *regs)
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{
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int recoverable = 0;
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char *exceptionMsg = "Unhandled ISR exception";
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exceptionMsg = IsrExceptions[regs->intNo];
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if (!recoverable) {
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KeStartPanic("[ISR 0x%x] Irrecoverable Kernel %s\n"
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" Error code : 0x%x\n"
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" RIP:\t\t%p\n"
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" CS:\t\t%p\n"
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" RFLAGS:\t%022b\n"
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" RSP:\t\t%p\n"
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" SS:\t\t%p\n",
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regs->intNo,
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exceptionMsg,
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regs->ErrorCode,
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regs->rip,
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regs->cs,
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regs->rflags,
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regs->rsp,
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regs->ss
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);
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} else {
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bprintf(BStdOut, "[ISR 0x%x] %s\n", regs->intNo, exceptionMsg);
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BStdOut->flusher(BStdOut);
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}
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}
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