Merge branch 'psx-spx:master' into system573

docs/cpuspecifications.md

@@ -165,6 +165,8 @@ but do not necessarily trigger exceptions if set to nonzero values.<br/>
 Load instructions can read from the data cache (if the data is not in the
 cache, or if the memory region is uncached, then the CPU gets halted until it
 has read the data) (however, the PSX doesn't have a data cache).<br/>
+Load and store instructions can generate address error exceptions if the memory address is not properly aligned (To a halfword boundary for lh/lhu/sh or a word boundary for lw/sw. lwl/lwr/swl/swr can't access misaligned address as they force align the memory address).
+Additionally, accessing certain invalid memory locations will cause a bus error exception. If an exception occurs during a load instruction, the rt register is left untouched.<br/>
 
 #### Caution - Load Delay
 The loaded data is NOT available to the next opcode, ie. the target register
@@ -349,10 +351,13 @@ Note that the instruction following the branch will always be executed.<br/>
   bgez   rs,dest     if rs>=0  then pc=$+4+(-8000h..+7FFFh)*4
   bgtz   rs,dest     if rs>0   then pc=$+4+(-8000h..+7FFFh)*4
   blez   rs,dest     if rs<=0  then pc=$+4+(-8000h..+7FFFh)*4
-  bltzal rs,dest     if rs<0   then pc=$+4+(..)*4, ra=$+8
-  bgezal rs,dest     if rs>=0  then pc=$+4+(..)*4, ra=$+8
+  bltzal rs,dest     if rs<0   then pc=$+4+(..)*4; ra=$+8; 
+  bgezal rs,dest     if rs>=0  then pc=$+4+(..)*4; ra=$+8;
 ```
 
+jr/jalr can be used to jump to an unaligned address, in which case an address error (AdEL) exception will be raised on the next instruction fetch.<br/>
+Additionally, bltzal/bgezal will always place the return address in $ra, whether or not the branch is taken. Additionally, if `rs` is $ra, then the value used for the comparison is $ra's value before linking.<br/>
+
 #### JALR cautions
 Caution: The JALR source code syntax varies (IDT79R3041 specs say "jalr rs,rd",
 but MIPS32 specs say "jalr rd,rs"). Moreover, JALR may not use the same

docs/dmachannels.md

@@ -26,7 +26,7 @@ enabled, in that case it does update MADR, same does probably also happen when
 getting interrupted by a higher priority DMA channel).<br/>
 In SyncMode=1 and SyncMode=2, the hardware does update MADR (it will contain
 the start address of the currently transferred block; at transfer end, it'll
-hold the end-address in SyncMode=1, or the 00FFFFFFh end-code in SyncMode=2)<br/>
+hold the end-address in SyncMode=1, or the end marker in SyncMode=2)<br/>
 Note: Address bit0-1 are writeable, but any updated current/end addresses are
 word-aligned with bit0-1 forced to zero.<br/>
 
@@ -154,6 +154,19 @@ XXX: DMA2 values 01000201h (VramWrite), 01000401h (List) aren't 100% confirmed
 to be used by ALL existing games. All other values are always used as listed
 above.<br/>
 
+#### Linked List DMA
+GPU data is often transferred from RAM to GP0 using DMA2 in linked list mode. In this mode,
+the DMA controller transfers words in "nodes", with the first node starting in the address indicated by D2_MADR.<br/>
+Each node is composed of a header word (the very first word in the node) and some extra words to be DMA'd before moving on to the next node. The node header is formatted like this:<br/>
+
+```
+  0-23  Address of the next node (or end marker)
+  24-31 Number of extra words to transfer for this node
+```
+
+If the address of the next node has bit 23 set, ie if `(address & 0x800000) != 0` then the DMA controller will not move on to the next node and the DMA transfer ends. In this case that address is commonly referred to as the "end marker" for the DMA.<br/>
+Commercial and homebrew games typically use 0xffffff as the end marker, however other values such as 0x800002, 0x934567, and so on will also do the trick assuming bit 23 is set.
+
 #### DMA Transfer Rates
 ```
   DMA0 MDEC.IN     1 clk/word   ;0110h clks per 100h words ;\plus whatever

docs/expansionportpio.md

@@ -456,8 +456,6 @@ The first write to 1F802070h is 32bit, all further writes seem to be 8bit.<br/>
 #### 1FA00000h - POST3 - External 7-segment Display (W) - PS2
 Similar to POST, but PS2 BIOS uses this address.<br/>
 
-
-
 ##   EXP2 Nocash Emulation Expansion
 #### 1F802060h Emu-Expansion ID1 "E" (R)
 #### 1F802061h Emu-Expansion ID2 "X" (R)
@@ -485,3 +483,26 @@ acknowledging the previous interrupt.<br/>
   2   Controller Turbo  (0=Normal, 1=Turbo)
   3-7 Reserved (must be zero)
 ```
+
+##   EXP2 PCSX-Redux Emulation Expansion
+PCSX-Redux contains some specific hardware registers for the purpose of testing and debugging.
+They are located past the 1F802080h address, which means that accessing them on the real
+hardware will cause an exception, unless the [1F80101Ch register](https://psx-spx.consoledev.net/memorycontrol/#1f80101ch-expansion-2-delaysize-usually-00070777h-128-bytes-8bit-bus) has been set to
+be at least twice its normal size.
+
+#### 1F802080h 4 Redux-Expansion ID "PCSX" (R)
+Identification string. Use this to query that your binary is running under PCSX-Redux.
+
+#### 1F802080h 1 Redux-Expansion Console putchar (W)
+Adds this character to the console output. This is an easier way to write to the console than using the BIOS.
+
+#### 1F802081h 1 Redux-Expansion Debug break (W)
+Causes a debug breakpoint to be triggered. PCSX-Redux will pause and the user will be alerted of a software breakpoint.
+
+#### 1F802082h 1 Redux-Expansion Exit code (W)
+Sets the exit code for the program. When in test mode, PCSX-Redux will exit with this code.
+
+#### 1F802084h 4 Redux-Expansion Notification message pointer (W)
+Displays a pop-up message to the user with the specified string.
+
+See [PCSX-Redux's documentation](https://pcsx-redux.consoledev.net/mips_api/) for more details and examples.

docs/graphicsprocessingunitgpu.md

@@ -231,8 +231,9 @@ Vertex     YYYYXXXX    - required, two signed 16 bits values
 When polyline mode is active, at least two vertices must be sent to the GPU.
 The vertex list is terminated by the bits 12-15 and 28-31 equaling `0x5`, or
 `(word & 0xF000F000) == 0x50005000`. The terminator value occurs on the first
-word of the vertex (i.e. the color word if it's a gouraud shaded).
+word of the vertex (i.e. the color word if it's a gouraud shaded).<br/>
 
+If the 2 vertices in a line overlap, then the GPU will draw a 1x1 rectangle in the location of the 2 vertices using the colour of the first vertex.<br/>
 
 #### Note
 Lines are displayed up to \<including\> their lower-right coordinates (ie.

docs/iomap.md

@@ -222,6 +222,14 @@
   1F802066h Emu-Expansion Halt (R)
   1F802067h Emu-Expansion Turbo Mode Flags (R/W)
 ```
+#### Expansion Region 2 - PCSX-Redux Emulation Expansion
+```
+  1F802080h 4 Redux-Expansion ID "PCSX" (R)
+  1F802080h 1 Redux-Expansion Console putchar (W)
+  1F802081h 1 Redux-Expansion Debug break (W)
+  1F802082h 1 Redux-Expansion Exit code (W)
+  1F802084h 4 Redux-Expansion Notification message pointer (W)
+```
 #### Expansion Region 3 (default 1 byte, max 2 MBytes)
 ```
   1FA00000h - Not used by BIOS or any PSX games