Cleaning up the assembly instructions a bit.
This commit is contained in:
Nicolas Noble
GitHub
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7e1e64f095
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63bc126f5f
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@ -156,11 +156,11 @@ but do not necessarily trigger exceptions if set to nonzero values.<br/>
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## CPU Load/Store Opcodes
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#### Load instructions
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```
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movbs rt,[imm+rs] lb rt,imm(rs) rt=[imm+rs] ;byte sign-extended
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movb rt,[imm+rs] lbu rt,imm(rs) rt=[imm+rs] ;byte zero-extended
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movhs rt,[imm+rs] lh rt,imm(rs) rt=[imm+rs] ;halfword sign-extended
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movh rt,[imm+rs] lhu rt,imm(rs) rt=[imm+rs] ;halfword zero-extended
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mov rt,[imm+rs] lw rt,imm(rs) rt=[imm+rs] ;word
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lb rt,imm(rs) rt=[imm+rs] ;byte sign-extended
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lbu rt,imm(rs) rt=[imm+rs] ;byte zero-extended
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lh rt,imm(rs) rt=[imm+rs] ;halfword sign-extended
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lhu rt,imm(rs) rt=[imm+rs] ;halfword zero-extended
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lw rt,imm(rs) rt=[imm+rs] ;word
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```
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Load instructions can read from the data cache (if the data is not in the
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cache, or if the memory region is uncached, then the CPU gets halted until it
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@ -176,9 +176,9 @@ next opcode would receive the NEW value).<br/>
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#### Store instructions
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```
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movb [imm+rs],rt sb rt,imm(rs) [imm+rs]=(rt AND FFh) ;store 8bit
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movh [imm+rs],rt sh rt,imm(rs) [imm+rs]=(rt AND FFFFh) ;store 16bit
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mov [imm+rs],rt sw rt,imm(rs) [imm+rs]=rt ;store 32bit
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sb rt,imm(rs) [imm+rs]=(rt AND FFh) ;store 8bit
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sh rt,imm(rs) [imm+rs]=(rt AND FFFFh) ;store 16bit
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sw rt,imm(rs) [imm+rs]=rt ;store 32bit
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```
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Store operations are passed to the write-buffer, so they can execute within a
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single clock cycle (unless the write-buffer was full, in that case the CPU gets
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@ -237,12 +237,12 @@ allowed... more PROBABLY that doesn't work?<br/>
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## CPU ALU Opcodes
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#### arithmetic instructions
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```
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addt rd,rs,rt add rd,rs,rt rd=rs+rt (with overflow trap)
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add rd,rs,rt addu rd,rs,rt rd=rs+rt
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subt rd,rs,rt sub rd,rs,rt rd=rs-rt (with overflow trap)
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sub rd,rs,rt subu rd,rs,rt rd=rs-rt
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addt rt,rs,imm addi rt,rs,imm rt=rs+(-8000h..+7FFFh) (with ov.trap)
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add rt,rs,imm addiu rt,rs,imm rt=rs+(-8000h..+7FFFh)
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add rd,rs,rt rd=rs+rt (with overflow trap)
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addu rd,rs,rt rd=rs+rt
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sub rd,rs,rt rd=rs-rt (with overflow trap)
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subu rd,rs,rt rd=rs-rt
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addi rt,rs,imm rt=rs+(-8000h..+7FFFh) (with ov.trap)
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addiu rt,rs,imm rt=rs+(-8000h..+7FFFh)
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```
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The opcodes "with overflow trap" do trigger an exception (and leave rd
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unchanged) in case of overflows.<br/>
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@ -257,38 +257,38 @@ unchanged) in case of overflows.<br/>
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#### logical instructions
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```
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and rd,rs,rt and rd,rs,rt rd = rs AND rt
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or rd,rs,rt or rd,rs,rt rd = rs OR rt
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xor rd,rs,rt xor rd,rs,rt rd = rs XOR rt
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nor rd,rs,rt nor rd,rs,rt rd = FFFFFFFFh XOR (rs OR rt)
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and rt,rs,imm andi rt,rs,imm rt = rs AND (0000h..FFFFh)
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or rt,rs,imm ori rt,rs,imm rt = rs OR (0000h..FFFFh)
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xor rt,rs,imm xori rt,rs,imm rt = rs XOR (0000h..FFFFh)
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and rd,rs,rt rd = rs AND rt
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or rd,rs,rt rd = rs OR rt
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xor rd,rs,rt rd = rs XOR rt
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nor rd,rs,rt rd = FFFFFFFFh XOR (rs OR rt)
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andi rt,rs,imm rt = rs AND (0000h..FFFFh)
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ori rt,rs,imm rt = rs OR (0000h..FFFFh)
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xori rt,rs,imm rt = rs XOR (0000h..FFFFh)
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```
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#### shifting instructions
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```
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shl rd,rt,rs sllv rd,rt,rs rd = rt SHL (rs AND 1Fh)
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shr rd,rt,rs srlv rd,rt,rs rd = rt SHR (rs AND 1Fh)
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sar rd,rt,rs srav rd,rt,rs rd = rt SAR (rs AND 1Fh)
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shl rd,rt,imm sll rd,rt,imm rd = rt SHL (00h..1Fh)
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shr rd,rt,imm srl rd,rt,imm rd = rt SHR (00h..1Fh)
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sar rd,rt,imm sra rd,rt,imm rd = rt SAR (00h..1Fh)
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mov rt,i*10000h lui rt,imm rt = (0000h..FFFFh) SHL 16
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sllv rd,rt,rs rd = rt SHL (rs AND 1Fh)
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srlv rd,rt,rs rd = rt SHR (rs AND 1Fh)
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srav rd,rt,rs rd = rt SAR (rs AND 1Fh)
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sll rd,rt,imm rd = rt SHL (00h..1Fh)
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srl rd,rt,imm rd = rt SHR (00h..1Fh)
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sra rd,rt,imm rd = rt SAR (00h..1Fh)
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lui rt,imm rt = (0000h..FFFFh) SHL 16
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```
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Unlike many other opcodes, shifts use 'rt' as second (not third) operand.<br/>
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The hardware does NOT generate exceptions on SHL overflows.<br/>
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#### Multiply/divide
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```
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smul rs,rt mult rs,rt hi:lo = rs*rt (signed)
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umul rs,rt multu rs,rt hi:lo = rs*rt (unsigned)
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sdiv rs,rt div rs,rt lo = rs/rt, hi=rs mod rt (signed)
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udiv rs,rt divu rs,rt lo = rs/rt, hi=rs mod rt (unsigned)
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mov rd,hi mfhi rd rd=hi ;move from hi
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mov rd,lo mflo rd rd=lo ;move from lo
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mov hi,rs mthi rs hi=rs ;move to hi
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mov lo,rs mtlo rs lo=rs ;move to lo
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mult rs,rt hi:lo = rs*rt (signed)
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multu rs,rt hi:lo = rs*rt (unsigned)
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div rs,rt lo = rs/rt, hi=rs mod rt (signed)
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divu rs,rt lo = rs/rt, hi=rs mod rt (unsigned)
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mfhi rd rd=hi ;move from hi
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mflo rd rd=lo ;move from lo
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mthi rs hi=rs ;move to hi
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mtlo rs lo=rs ;move to lo
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```
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The mul/div opcodes are starting the multiply/divide operation, starting takes
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only a single clock cycle, however, trying to read the result from the hi/lo
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@ -315,10 +315,10 @@ The hardware does NOT generate exceptions on divide overflows, instead, divide
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errors are returning the following values:<br/>
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```
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Opcode Rs Rd Hi/Remainder Lo/Result
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udiv 0..FFFFFFFFh 0 --> Rs FFFFFFFFh
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sdiv 0..+7FFFFFFFh 0 --> Rs -1
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sdiv -80000000h..-1 0 --> Rs +1
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sdiv -80000000h -1 --> 0 -80000000h
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divu 0..FFFFFFFFh 0 --> Rs FFFFFFFFh
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div 0..+7FFFFFFFh 0 --> Rs -1
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div -80000000h..-1 0 --> Rs +1
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div -80000000h -1 --> 0 -80000000h
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```
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For udiv, the result is more or less correct (as close to infinite as
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possible). For sdiv, the results are total garbage (about farthest away from
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@ -333,18 +333,18 @@ yet understood if/when/how that rule applies...?<br/>
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#### jumps and branches
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Note that the instruction following the branch will always be executed.<br/>
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```
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jmp dest j dest pc=(pc and F0000000h)+(imm26bit*4)
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call dest jal dest pc=(pc and F0000000h)+(imm26bit*4),ra=$+8
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jmp rs jr rs pc=rs
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call rs,ret=rd jalr (rd,)rs(,rd) pc=rs, rd=$+8 ;see caution
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je rs,rt,dest beq rs,rt,dest if rs=rt then pc=$+4+(-8000h..+7FFFh)*4
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jne rs,rt,dest bne rs,rt,dest if rs<>rt then pc=$+4+(-8000h..+7FFFh)*4
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js rs,dest bltz rs,dest if rs<0 then pc=$+4+(-8000h..+7FFFh)*4
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jns rs,dest bgez rs,dest if rs>=0 then pc=$+4+(-8000h..+7FFFh)*4
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jgtz rs,dest bgtz rs,dest if rs>0 then pc=$+4+(-8000h..+7FFFh)*4
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jlez rs,dest blez rs,dest if rs<=0 then pc=$+4+(-8000h..+7FFFh)*4
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calls rs,dest bltzal rs,dest if rs<0 then pc=$+4+(..)*4, ra=$+8
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callns rs,dest bgezal rs,dest if rs>=0 then pc=$+4+(..)*4, ra=$+8
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j dest pc=(pc and F0000000h)+(imm26bit*4)
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jal dest pc=(pc and F0000000h)+(imm26bit*4),ra=$+8
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jr rs pc=rs
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jalr (rd,)rs(,rd) pc=rs, rd=$+8 ;see caution
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beq rs,rt,dest if rs=rt then pc=$+4+(-8000h..+7FFFh)*4
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bne rs,rt,dest if rs<>rt then pc=$+4+(-8000h..+7FFFh)*4
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bltz rs,dest if rs<0 then pc=$+4+(-8000h..+7FFFh)*4
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bgez rs,dest if rs>=0 then pc=$+4+(-8000h..+7FFFh)*4
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bgtz rs,dest if rs>0 then pc=$+4+(-8000h..+7FFFh)*4
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blez rs,dest if rs<=0 then pc=$+4+(-8000h..+7FFFh)*4
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bltzal rs,dest if rs<0 then pc=$+4+(..)*4, ra=$+8
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bgezal rs,dest if rs>=0 then pc=$+4+(..)*4, ra=$+8
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```
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#### JALR cautions
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@ -371,17 +371,17 @@ interprete it by software; by examing the opcode bits at [epc-4]).<br/>
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## CPU Coprocessor Opcodes
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#### Coprocessor Instructions (COP0..COP3)
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```
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mov rt,cop#Rd(0-31) mfc# rt,rd ;rt = cop#datRd ;data regs
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mov rt,cop#Rd(32-63) cfc# rt,rd ;rt = cop#cntRd ;control regs
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mov cop#Rd(0-31),rt mtc# rt,rd ;cop#datRd = rt ;data regs
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mov cop#Rd(32-63),rt ctc# rt,rd ;cop#cntRd = rt ;control regs
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mov cop#cmd,imm25 cop# imm25 ;exec cop# command 0..1FFFFFFh
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mov cop#Rt(0-31),[rs+imm] lwc# rt,imm(rs) ;cop#dat_rt = [rs+imm] ;word
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mov [rs+imm],cop#Rt(0-31) swc# rt,imm(rs) ;[rs+imm] = cop#dat_rt ;word
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jf cop#flg,dest bc#f dest ;if cop#flg=false then pc=$+disp
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jt cop#flg,dest bc#t dest ;if cop#flg=true then pc=$+disp
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rfe rfe ;return from exception (COP0)
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tlb<xx> tlb<xx> ;virtual memory related (COP0)
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mfc# rt,rd ;rt = cop#datRd ;data regs
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cfc# rt,rd ;rt = cop#cntRd ;control regs
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mtc# rt,rd ;cop#datRd = rt ;data regs
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ctc# rt,rd ;cop#cntRd = rt ;control regs
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cop# imm25 ;exec cop# command 0..1FFFFFFh
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lwc# rt,imm(rs) ;cop#dat_rt = [rs+imm] ;word
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swc# rt,imm(rs) ;[rs+imm] = cop#dat_rt ;word
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bc#f dest ;if cop#flg=false then pc=$+disp
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bc#t dest ;if cop#flg=true then pc=$+disp
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rfe ;return from exception (COP0)
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tlb<xx> ;virtual memory related (COP0)
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```
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Unknown if any tlb-opcodes (tlbr,tlbwi,tlbwr,tlbp) are implemented in the psx?<br/>
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