[CPU] Correct write-queue section
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@ -181,10 +181,9 @@ MFC2/CFC2 also have a 1-instruction delay until the target register is loaded wi
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sh rt,imm(rs) [imm+rs]=(rt AND FFFFh) ;store 16bit
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sh rt,imm(rs) [imm+rs]=(rt AND FFFFh) ;store 16bit
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sw rt,imm(rs) [imm+rs]=rt ;store 32bit
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sw rt,imm(rs) [imm+rs]=rt ;store 32bit
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```
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```
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Store operations are passed to the write-buffer, so they can execute within a
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Store operations are passed to the write-queue, so they can execute within a
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single clock cycle (unless the write-buffer was full, in that case the CPU gets
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single clock cycle (unless the write-queue was full, in that case the CPU gets
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halted until there's room in the buffer). But, the PSX doesn't have a
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halted until there's room in the queue). For more information on the write-queue, visit [this page](https://psx-spx.consoledev.net/memorymap/#write-queue).<br/>
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writebuffer...?<br/>
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#### Load/Store Alignment
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#### Load/Store Alignment
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Halfword addresses must be aligned by 2, word addresses must be aligned by 4,
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Halfword addresses must be aligned by 2, word addresses must be aligned by 4,
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