573 lines
26 KiB
HTML
573 lines
26 KiB
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PlayStation Specifications - psx-spx
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Memory Map
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PlayStation Specifications - psx-spx
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GitHub
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Home
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Memory Map
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<a class="md-nav__link md-nav__link--active" href="./">
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Memory Map
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</a>
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<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
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<label class="md-nav__title" for="__toc">
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Table of contents
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<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
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<li class="md-nav__item">
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<a class="md-nav__link" href="#memory-map_1">
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Memory Map
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#additional-memory-not-mapped-to-the-cpu-bus">
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Additional Memory (not mapped to the CPU bus)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#kusegkseg0kseg1kseg2-memory-regions">
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KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#i-cache">
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i-Cache
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#scratchpad">
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Scratchpad
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#memory-mirrors">
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Memory Mirrors
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#memory-exceptions">
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Memory Exceptions
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#write-queue">
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Write queue
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#more-memory-info">
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More Memory Info
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</a>
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</li>
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</ul>
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</nav>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../iomap/">
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I/O Map
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../graphicsprocessingunitgpu/">
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Graphics Processing Unit (GPU)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../geometrytransformationenginegte/">
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Geometry Transformation Engine (GTE)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../macroblockdecodermdec/">
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Macroblock Decoder (MDEC)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../soundprocessingunitspu/">
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Sound Processing Unit (SPU)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../interrupts/">
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Interrupts
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../dmachannels/">
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DMA Channels
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../timers/">
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Timers
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../cdromdrive/">
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CDROM Drive
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../controllersandmemorycards/">
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Controllers and Memory Cards
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../pocketstation/">
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Pocketstation
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../serialportsio/">
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Serial Port (SIO)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../expansionportpio/">
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Expansion Port (PIO)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../memorycontrol/">
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Memory Control
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../unpredictablethings/">
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Unpredictable Things
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../cpuspecifications/">
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CPU Specifications
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../kernelbios/">
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Kernel (BIOS)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../arcadecabinets/">
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Arcade Cabinets
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../cheatdevices/">
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Cheat Devices
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../psxdevboardchipsets/">
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PSX Dev-Board Chipsets
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../hardwarenumbers/">
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Hardware Numbers
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../pinouts/">
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Pinouts
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../aboutcredits/">
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About & Credits
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../cdromvideocdsvcd/">
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CDROM Video CDs (VCD)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
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CDROM Internal Info on PSX CDROM Controller
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</a>
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</li>
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</ul>
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</nav>
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</div>
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</div>
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</div>
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<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
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<div class="md-sidebar__scrollwrap">
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<div class="md-sidebar__inner">
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<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
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<label class="md-nav__title" for="__toc">
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<span class="md-nav__icon md-icon"></span>
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Table of contents
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</label>
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<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
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<li class="md-nav__item">
|
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<a class="md-nav__link" href="#memory-map_1">
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Memory Map
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</a>
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</li>
|
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<li class="md-nav__item">
|
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<a class="md-nav__link" href="#additional-memory-not-mapped-to-the-cpu-bus">
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Additional Memory (not mapped to the CPU bus)
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</a>
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</li>
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<li class="md-nav__item">
|
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<a class="md-nav__link" href="#kusegkseg0kseg1kseg2-memory-regions">
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KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions
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</a>
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</li>
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i-Cache
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Scratchpad
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Memory Mirrors
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Memory Exceptions
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Write queue
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More Memory Info
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<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/memorymap.md" title="Edit this page">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
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<h1 id="memory-map">Memory Map</h1>
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<h4 id="memory-map_1">Memory Map</h4>
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<pre><code> KUSEG KSEG0 KSEG1
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00000000h 80000000h A0000000h 2048K Main RAM (first 64K reserved for BIOS)
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1F000000h 9F000000h BF000000h 8192K Expansion Region 1 (ROM/RAM)
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1F800000h 9F800000h -- 1K Scratchpad (D-Cache used as Fast RAM)
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1F801000h 9F801000h BF801000h 8K I/O Ports
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1F802000h 9F802000h BF802000h 8K Expansion Region 2 (I/O Ports)
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1FA00000h 9FA00000h BFA00000h 2048K Expansion Region 3 (SRAM BIOS region for DTL cards)
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1FC00000h 9FC00000h BFC00000h 512K BIOS ROM (Kernel) (4096K max)
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FFFE0000h (in KSEG2) 0.5K Internal CPU control registers (Cache Control)
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</code></pre>
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<p>Additionally, there are a number of memory mirrors.<br/></p>
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<h4 id="additional-memory-not-mapped-to-the-cpu-bus">Additional Memory (not mapped to the CPU bus)</h4>
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<pre><code> 1024K VRAM (Framebuffers, Textures, Palettes) (with 2KB Texture Cache)
|
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512K Sound RAM (Capture Buffers, ADPCM Data, Reverb Workspace)
|
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0.5K CDROM controller RAM (see CDROM Test commands)
|
|
16.5K CDROM controller ROM (Firmware and Bootstrap for MC68HC05 cpu)
|
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32K CDROM Buffer (IC303) (32Kx8) (BUG: only two sectors accessible?)
|
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128K External Memory Card(s) (EEPROMs)
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</code></pre>
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<h4 id="kusegkseg0kseg1kseg2-memory-regions">KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions</h4>
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<pre><code> Address Name i-Cache Write-Queue
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00000000h KUSEG Yes Yes
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80000000h KSEG0 Yes Yes
|
|
A0000000h KSEG1 No No
|
|
C0000000h KSEG2 (No code) No
|
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</code></pre>
|
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<p>Kernel Memory: KSEG1 is the normal physical memory (uncached), KSEG0 is a
|
|
mirror thereof (but with cache enabled). KSEG2 is usually intended to contain
|
|
virtual kernel memory, but in the PSX it's containing Cache Control hardware registers.<br/>
|
|
User Memory: KUSEG is intended to contain 2GB virtual memory (on extended MIPS
|
|
processors), the PSX doesn't support virtual memory, and KUSEG simply contains
|
|
a mirror of KSEG0/KSEG1 (in the first 512MB) (trying to access memory in the
|
|
remaining 1.5GB causes an exception).<br/></p>
|
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<h4 id="i-cache">i-Cache</h4>
|
|
<p>The i-Cache can hold 4096 bytes, or 1024 instructions.<br/>
|
|
It is only active in the cached regions (KUSEG and KSEG0).<br/>
|
|
There are reportedly some restrictions... not sure there... eventually it is
|
|
using the LSBs of the address as cache-line number... so, for example, it
|
|
couldn't simultaneously memorize opcodes at BOTH address 80001234h, AND at
|
|
address 800F1234h (?)<br/></p>
|
|
<h4 id="scratchpad">Scratchpad</h4>
|
|
<p>MIPS CPUs usually have a d-Cache, but, in the PSX, Sony has assigned it as
|
|
what's referenced as the "Scratchpad", mapped to a fixed memory location at
|
|
1F800000h..1F8003FFh, ie. it's used as Fast RAM, rather than as cache.<br/>
|
|
There \<might> be a way to disable that behavior (via Port FFFE0130h or
|
|
so), but, the Kernel is accessing I/O ports via KUSEG, so activating Data Cache
|
|
would cause the Kernel to access cached I/O ports.<br/>
|
|
The purpose of the scratchpad is to have a more flexible cache system available
|
|
to the programmer. Neither the kernel nor the Sony libraries will try to make use
|
|
of it, so it is therefore completely up for grabs to the programmer. A good example
|
|
would be if you were to write a piece of code that's doing a lot of CRC computation,
|
|
to use the 1KB scratchpad to initially load the CRC lookup tables, which incidentally,
|
|
is exactly 1KB large. Doing this will relieve SDRAM page changes overhead while reading
|
|
the data to checksum linearly, while also keeping the whole CRC code in the i-Cache,
|
|
hence being more optimal than what you'd get with an automatic d-Cache system.</p>
|
|
<h4 id="memory-mirrors">Memory Mirrors</h4>
|
|
<p>As described above, the 512Mbyte KUSEG, KSEG0, and KSEG1 regions are mirrors of
|
|
each other. Additional mirrors within these 512MB regions are:<br/></p>
|
|
<pre><code> 2MB RAM can be mirrored to the first 8MB (strangely, enabled by default)
|
|
512K BIOS ROM can be mirrored to the last 4MB (disabled by default)
|
|
Expansion hardware (if any) may be mirrored within expansion region
|
|
The seven DMA Control Registers at 1F8010x8h are mirrored to 1F8010xCh
|
|
</code></pre>
|
|
<p>The size of the RAM, BIOS, Expansion regions can be configured by software, for
|
|
Expansion Region it's also possible to change base address, see:<br/>
|
|
<a href="../memorycontrol/">Memory Control</a><br/>
|
|
The Scratchpad is mirrored only in KUSEG and KSEG0, but not in KSEG1.<br/></p>
|
|
<h4 id="memory-exceptions">Memory Exceptions</h4>
|
|
<pre><code> Memory Error ------> Misalignments
|
|
(and probably also KSEG access in User mode)
|
|
Bus Error ------> Unused Memory Regions (including Gaps in I/O Region)
|
|
(unless RAM/BIOS/Expansion mirrors are mapped to "unused" area)
|
|
</code></pre>
|
|
<h4 id="write-queue">Write queue</h4>
|
|
<p>The MIPS CPU has a 4-words deep pass-through write queue, in order to relieve
|
|
some bus contention when writing to memory. If reading the same memory location
|
|
that just got written into the write queue, it will first be flushed before
|
|
being read back from memory.<br/>
|
|
It is important to realize that the write queue's mechanism is only viable for
|
|
normal memory attached to the main CPU, and that any hardware register state machine
|
|
will get messed up by it.<br/>
|
|
The typical example is the typical JEDEC standard to access flash, which usually does
|
|
the following sequence to read the ID of a flash chip:</p>
|
|
<pre><code class="language-C"> base[0xAAA] = 0xAA;
|
|
base[0x555] = 0x55;
|
|
base[0xAAA] = 0x90;
|
|
uint8_t mnfctrID = base[0x000];
|
|
uint8_t deviceId = base[0x002];
|
|
</code></pre>
|
|
<p>In this example above, if <code>base</code> is located in a memory segment that has the write queue
|
|
enabled, even if the low level assembly code will do the first 3 stores before doing 2 loads,
|
|
the physical signals sent to that device through the CPU bus will be seen in the sequence:</p>
|
|
<pre><code>store(0xaaa, 0xaa)
|
|
load(0x000)
|
|
store(0x555, 0x55)
|
|
load(0x002)
|
|
store(0xaaa, 0x90)
|
|
</code></pre>
|
|
<p>Therefore, using KSEG1 that disables the write queue is the only way to ensure that the
|
|
operations are done in the proper way.</p>
|
|
<p>The above is valid for most of the hardware connected to the main CPU, such as the CDROM
|
|
controller, exp1, exp2, the SPU, or the GPU. Therefore, using BF80180xh to access the
|
|
CDROM registers is more correct than using 1F80180xh.</p>
|
|
<p>It is noteworthy that the Sony code will still incorrectly use KUSEG as the memory map
|
|
for all hardware registers, and they then spend a lot of time writing 4 dummy values
|
|
somewhere, in order to ensure the write queue has been flushed.</p>
|
|
<p>The SN debugger in contrast is properly using the KSEG1 memory map for all the hardware
|
|
registers, nullifying the need to flush the write queue when accessing it.</p>
|
|
<p>It's also noteworthy that doing ANY KSEG1 access (read OR write) will automatically stall
|
|
the CPU in order to flush the whole write queue before proceeding with the operation.
|
|
Therefore, all BIOS ROM operations will naturally and effectively have the write queue
|
|
disabled, as this code requires the CPU to read from KSEG1 constantly.</p>
|
|
<p>This also means that if using KUSEG for the hardware registers, another method to flush
|
|
the write queue, albeit potentially slightly less efficient, would be to simply read
|
|
the first byte located at BFC00000h. The latter is what is effectively described as the
|
|
official method to flush the write queue in the MIPS handbook. This could be potentially
|
|
useful to flush the write queue all at once, instead of flushing it word by word.</p>
|
|
<h4 id="more-memory-info">More Memory Info</h4>
|
|
<p>For Info on Exception vectors, Unused/Garbage memory locations, I/O Ports,
|
|
Expansion ROM Headers, and Memory Waitstate Control, etc. see:<br/>
|
|
<a href="../iomap/">I/O Map</a><br/>
|
|
<a href="../memorycontrol/">Memory Control</a><br/>
|
|
<a href="../expansionportpio/#exp1-expansion-rom-header">EXP1 Expansion ROM Header</a><br/>
|
|
<a href="../kernelbios/#bios-memory-map">BIOS Memory Map</a><br/>
|
|
<a href="../kernelbios/#bios-memory-allocation">BIOS Memory Allocation</a><br/>
|
|
<a href="../cpuspecifications/#cop0-exception-handling">COP0 - Exception Handling</a><br/>
|
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<a href="../unpredictablethings/">Unpredictable Things</a><br/></p>
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