2019-05-22 18:39:46 +02:00
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// The OS/K Team licenses this file to you under the MIT license.
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// See the LICENSE file in the project root for more information.
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2019-06-05 12:53:09 +02:00
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#include <pc/arch.h>
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2019-05-22 18:39:46 +02:00
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2019-06-13 15:00:48 +02:00
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//----------------------------------------------------------------------------//
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2019-05-22 18:39:46 +02:00
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2019-05-29 19:00:13 +02:00
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#define CHK_ALIGN(type) \
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if (addr % alignof(type) > 0) { \
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_except(ctx, E_ALI, \
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"Non-aligned memory access: 0x%012lX (0x%012lX) by %lu", \
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addr, real, alignof(type)); \
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2019-05-22 18:39:46 +02:00
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}
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2019-05-29 19:00:13 +02:00
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2019-06-13 15:00:48 +02:00
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//----------------------------------------------------------------------------//
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2019-05-29 19:00:13 +02:00
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2019-06-13 15:00:48 +02:00
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static ulong readmem8(ctx_t *ctx, ulong real, ulong addr)
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2019-05-29 19:00:13 +02:00
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{
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2019-05-29 16:57:22 +02:00
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if (addr % 2 == 0) return (ulong)ctx->mp[real] & 0xFF;
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2019-05-22 18:39:46 +02:00
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else return ((ulong)ctx->mp[real] & 0xFF00) >> 8;
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}
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2019-06-13 15:00:48 +02:00
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static ulong readmem16(ctx_t *ctx, ulong real, ulong addr)
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2019-05-22 18:39:46 +02:00
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{
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CHK_ALIGN(ushort);
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2019-05-22 18:39:46 +02:00
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return (ulong)ctx->mp[real];
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}
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2019-06-13 15:00:48 +02:00
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static ulong readmem32(ctx_t *ctx, ulong real, ulong addr)
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{
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CHK_ALIGN(uint);
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ulong val = ctx->mp[real++];
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val = val | ((ulong)ctx->mp[real] << 16);
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2019-05-30 12:44:56 +02:00
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2019-05-22 18:39:46 +02:00
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return val;
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}
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2019-06-13 15:00:48 +02:00
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static ulong readmem64(ctx_t *ctx, ulong real, ulong addr)
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2019-05-22 18:39:46 +02:00
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{
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2019-05-29 19:00:13 +02:00
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CHK_ALIGN(ulong);
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2019-05-22 18:39:46 +02:00
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ulong val = (ulong)ctx->mp[real++];
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2019-05-29 16:57:22 +02:00
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val = val | ((ulong)ctx->mp[real++] << 16);
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val = val | ((ulong)ctx->mp[real++] << 32);
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val = val | ((ulong)ctx->mp[real] << 48);
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2019-05-30 12:44:56 +02:00
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2019-05-22 18:39:46 +02:00
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return val;
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}
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2019-06-13 15:00:48 +02:00
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//----------------------------------------------------------------------------//
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2019-05-22 18:39:46 +02:00
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2019-06-13 15:00:48 +02:00
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static void writemem8(ctx_t *ctx, ulong val, ulong real, ulong addr)
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{
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ushort v = ctx->mp[real];
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2019-05-30 19:07:04 +02:00
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if (!(addr % 2)) {
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2019-05-22 18:39:46 +02:00
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ctx->mp[real] = (v & 0xFF00) | (val & 0xFF);
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}
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2019-05-30 12:44:56 +02:00
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else {
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ctx->mp[real] = (v & 0xFF) | (((val & 0xFF) << 8));
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}
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}
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2019-06-13 15:00:48 +02:00
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static void writemem16(ctx_t *ctx, ulong val, ulong real, ulong addr)
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{
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CHK_ALIGN(ushort);
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2019-05-22 18:39:46 +02:00
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ctx->mp[real] = val & 0xFFFF;
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}
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static void writemem32(ctx_t *ctx, ulong val, ulong real, ulong addr)
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{
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CHK_ALIGN(uint);
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2019-05-22 18:39:46 +02:00
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2019-05-29 16:57:22 +02:00
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ctx->mp[real++] = val & 0xFFFF;
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ctx->mp[real] = (val >> 16) & 0xFFFF;
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2019-05-22 18:39:46 +02:00
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}
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2019-06-13 15:00:48 +02:00
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static void writemem64(ctx_t *ctx, ulong val, ulong real, ulong addr)
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2019-05-22 18:39:46 +02:00
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{
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CHK_ALIGN(ulong);
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2019-05-22 18:39:46 +02:00
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2019-05-29 16:57:22 +02:00
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ctx->mp[real++] = val;
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2019-05-22 18:39:46 +02:00
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ctx->mp[real++] = (val >> 16) & 0xFFFF;
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2019-05-29 16:57:22 +02:00
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ctx->mp[real++] = (val >> 32) & 0xFFFF;
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ctx->mp[real] = (val >> 48) & 0xFFFF;
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2019-05-22 18:39:46 +02:00
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}
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2019-05-29 16:57:22 +02:00
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2019-06-13 15:00:48 +02:00
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//----------------------------------------------------------------------------//
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#define CHK_RANGE() \
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if (addr < MEMOFF || real >= MEMSIZE) { \
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_except(ctx, E_ACC, \
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"Invalid MEM access: 0x%012lX (0x%012lX)", addr, real); \
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}
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#define GETREAL() \
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addr += cr2; \
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ulong real = addr2real(addr)
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#define SIGN_EXTEND(val, mask) \
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(val & ((mask + 1) >> 1) \
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? (val | ~mask) \
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: val)
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//----------------------------------------------------------------------------//
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ulong readmem(ctx_t *ctx, ulong addr, uint len)
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{
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GETREAL();
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CHK_RANGE();
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ulong val;
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switch (len) {
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case 1:
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val = readmem8(ctx, real, addr);
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val = SIGN_EXTEND(val, 0xFF);
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break;
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case 2:
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val = readmem16(ctx, real, addr);
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val = SIGN_EXTEND(val, 0xFFFF);
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break;
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case 4:
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val = readmem32(ctx, real, addr);
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val = SIGN_EXTEND(val, 0xFFFFFFFFUL);
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break;
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case 8:
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return readmem64(ctx, real, addr);
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default: log("readmem() bad length %d!\n", len); abort();
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}
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return val;
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}
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void writemem(ctx_t *ctx, ulong val, ulong addr, uint len)
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{
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GETREAL();
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CHK_RANGE();
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switch (len) {
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case 1: writemem8(ctx, val, real, addr); break;
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case 2: writemem16(ctx, val, real, addr); break;
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case 4: writemem32(ctx, val, real, addr); break;
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case 8: writemem64(ctx, val, real, addr); break;
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default: log("writemem() bad length %d!\n", len); abort();
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}
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}
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//----------------------------------------------------------------------------//
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//
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// The following functions zero-extend rather than sign-extend
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//
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ulong readmemzx(ctx_t *ctx, ulong addr, uint len)
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{
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GETREAL();
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CHK_RANGE();
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switch (len) {
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case 1: return readmem8(ctx, real, addr); break;
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case 2: return readmem16(ctx, real, addr); break;
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case 4: return readmem32(ctx, real, addr); break;
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case 8: return readmem64(ctx, real, addr); break;
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default: log("readmem() bad length %d!\n", len); abort();
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}
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}
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void writememzx(ctx_t *ctx, ulong val, ulong addr, uint len)
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{
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GETREAL();
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CHK_RANGE();
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switch (len) {
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case 1: writemem8(ctx, val, real, addr); break;
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case 2: writemem16(ctx, val, real, addr); break;
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case 4: writemem32(ctx, val, real, addr); break;
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case 8: writemem64(ctx, val, real, addr); break;
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default: log("writemem() bad length %d!\n", len); abort();
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}
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}
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