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Fixed PCI config base address error
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parent
65312af6dc
commit
9930a45163
2
Makefile
2
Makefile
@ -272,7 +272,7 @@ all :
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test: all installonimage
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@qemu-system-x86_64 -vga std -enable-kvm -machine type=q35 -soundhw pcspk -cpu host -s \
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-rtc base=localtime -m $(ram) -hda $(installdisk) \
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-rtc base=localtime -m $(ram) -hda $(installdisk) -net nic,model=rtl8139 \
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-d cpu_reset,guest_errors,pcall,int 2> $(BUILDDIR)/qemu.log &
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run: test
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@ -196,7 +196,7 @@ struct FADT_t
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//----------------------------------------------------------------------------//
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struct SDT_MCFG_t {
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struct MCFG_t {
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char signature[4];
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uint length;
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uchar revision;
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@ -209,7 +209,7 @@ struct SDT_MCFG_t {
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ulong reserved;
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void* pciConfigBaseAddress;
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};
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} __attribute__ ((packed));
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//----------------------------------------------------------------------------//
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@ -44,25 +44,13 @@ static inline void* pciGetConfigAddr(uchar bus, uchar device, uchar function, us
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KernLog("pciGetConfigAddr(): bad register offset\n");
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return 0;
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}
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ulong addr = bus*32*8*4096 + device*8*4096 + function*4096 + offset + (ulong)pciConfigBaseAddress;
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// DEBUG
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KernLog("bus: %u\n", bus);
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KernLog("device: %u\n", device);
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KernLog("function: %u\n", function);
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KernLog("offset: %u\n", offset);
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KernLog("ADDR: %lx\n", addr);
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KernLog("ADDR: %p\n", (void*)addr);
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return (void*)addr;
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return (void*)(bus*32*8*4096 + device*8*4096 + function*4096 + offset + (ulong)pciConfigBaseAddress);
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}
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uchar pciReadConfigByte(uchar bus, uchar device, uchar function, ushort offset)
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{
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uchar *ptr = (uchar*)(pciGetConfigAddr(bus, device, function, offset));
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KernLog("ADDR_uchar*: %p\n", ptr);
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uchar value = *ptr;
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//KernLog("VALUE: %u\n\n", value);
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return *ptr;
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return *((uchar*)(pciGetConfigAddr(bus, device, function, offset)));
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}
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ushort pciReadConfigWord(uchar bus, uchar device, uchar function, ushort offset)
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@ -81,34 +69,28 @@ void pciScanAll()
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KernLog("Unable to access PCI configuration : MCFG table not reachable\n");
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return;
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}
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//KernLog("%x", pciReadConfigByte(0, 0, 0, 0));
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uchar byte = pciReadConfigByte(0, 0, 0, 0);
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/*
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for(uchar bus = 0; bus < 256; bus++) {
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for(uchar bus = 0; bus < 255; bus++) {
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for(uchar device = 0; device < 32; device++) {
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for(uchar function = 0; function < 8; function++) {
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ushort vendor = pciReadWord(bus, device, function, PCI_REG_VENDOR);
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ushort vendor = pciReadConfigWord(bus, device, function, PCI_REG_VENDOR);
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if(vendor == 0xffff) continue;
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KernLog("PCI device found ! vendor: %x, device: %x\n", vendor, pciReadWord(bus, device, function, PCI_REG_DEVICE));
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DebugLog("PCI device found ! vendor: %x, device: %x\n", vendor, pciReadConfigWord(bus, device, function, PCI_REG_DEVICE));
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}
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}
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}
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*/
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}
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void IoInitPCI()
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{
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struct SDT_MCFG_t *MCFG_table = (struct SDT_MCFG_t*)IoGetAcpiTable(SDT_MCFG);
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struct MCFG_t *MCFG_table = (struct MCFG_t*)IoGetAcpiTable(SDT_MCFG);
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if(MCFG_table == NULL) {
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KernLog("Unable to access PCI configuration : MCFG table not reachable\n");
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}
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pciConfigBaseAddress = MCFG_table->pciConfigBaseAddress;
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DebugLog("PCI Config Base address = 0x%p\n", pciConfigBaseAddress);
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// 0x ff00 0000 0000 0000
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MmMapPage(pciConfigBaseAddress, pciConfigBaseAddress + 256*1024*1024, PRESENT | READWRITE);
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pciScanAll();
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}
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