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Merge branch 'pci' into disk
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commit
b5c1f78104
@ -35,11 +35,18 @@
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//
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// Device registers offsets
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//
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#define PCI_REG_VENDOR 0
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#define PCI_REG_DEVICE 2
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#define PCI_REG_COMMAND 4
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#define PCI_REG_STATUS 6
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//..
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#define PCI_REG_VENDOR 0x00
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#define PCI_REG_DEVICE 0x02
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#define PCI_REG_COMMAND 0x04
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#define PCI_REG_STATUS 0x06
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#define PCI_REG_REVISION 0x08
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#define PCI_REG_PROGIF 0x09
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#define PCI_REG_SUBCLASS 0x0A
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#define PCI_REG_CLASS 0x0B
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#define PCI_REG_CACHE_LINE_SIZE 0x0C
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#define PCI_REG_LATENCY_TIMER 0x0D
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#define PCI_REG_HEADER_TYPE 0x0E
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#define PCI_REG_BIST 0x0F
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#define PCI_REG_BAR0 0x10
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#define PCI_REG_BAR1 0x14
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#define PCI_REG_BAR2 0x18
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@ -57,6 +64,10 @@
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struct PciDev_t {
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ushort vendorID;
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ushort deviceID;
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uchar classID;
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uchar subclassID;
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void* configAddr;
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};
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@ -115,7 +115,9 @@ void IoPciEnumerate()
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for(uchar function = 0; function < 8; function++) {
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ushort vendor = pciReadConfigWord((uchar)bus, device, function, PCI_REG_VENDOR);
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if(vendor == 0xffff) continue;
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DebugLog("PCI device vendor: %x, device: %x\n",
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DebugLog("PCI device class: %x, subclass: %x, vendor: %x, device: %x\n",
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pciReadConfigByte((uchar)bus, device, function, PCI_REG_CLASS),
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pciReadConfigByte((uchar)bus, device, function, PCI_REG_SUBCLASS),
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vendor,
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pciReadConfigWord((uchar)bus, device, function, PCI_REG_DEVICE)
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);
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@ -157,8 +159,6 @@ void IoInitPCI()
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pciConfigBaseAddress = MCFG_table->pciConfigBaseAddress;
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DebugLog("PCI Config Base address = 0x%p\n", pciConfigBaseAddress);
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IoPciEnumerate();
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// Give R/W access to the configuration space
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int maxI = (256 * 32 * 8 * 4096) / KPAGESIZE;
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for(int i=0; i < maxI; i++)
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@ -167,4 +167,6 @@ void IoInitPCI()
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(void *)((ulong)pciConfigBaseAddress + i * KPAGESIZE),
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PRESENT | READWRITE);
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}
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IoPciEnumerate();
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}
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