643 lines
30 KiB
HTML
643 lines
30 KiB
HTML
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<!DOCTYPE html>
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<html class="no-js" lang="en">
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<head>
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<meta charset="utf-8"/>
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<meta content="width=device-width,initial-scale=1" name="viewport"/>
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<link href="https://psx-spx.consoledev.net/dmachannels/" rel="canonical"/>
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<link href="../assets/images/favicon.png" rel="icon"/>
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<meta content="mkdocs-1.1.2, mkdocs-material-7.1.3" name="generator"/>
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<title>DMA Channels - PlayStation Specifications - psx-spx</title>
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<link href="../assets/stylesheets/main.e35208c4.min.css" rel="stylesheet"/>
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<link href="../assets/stylesheets/palette.ef6f36e2.min.css" rel="stylesheet"/>
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<link crossorigin="" href="https://fonts.gstatic.com" rel="preconnect"/>
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<link href="https://fonts.googleapis.com/css?family=Roboto:300,400,400i,700%7CRoboto+Mono&display=fallback" rel="stylesheet"/>
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<style>:root{--md-text-font-family:"Roboto";--md-code-font-family:"Roboto Mono"}</style>
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<link href="../css/extra.css" rel="stylesheet"/>
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</head>
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<body data-md-color-accent="indigo" data-md-color-primary="indigo" data-md-color-scheme="default" dir="ltr">
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<script>function __prefix(e){return new URL("..",location).pathname+"."+e}function __get(e,t=localStorage){return JSON.parse(t.getItem(__prefix(e)))}</script>
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<script>var palette=__get("__palette");if(null!==palette&&"object"==typeof palette.color)for(var key in palette.color)document.body.setAttribute("data-md-color-"+key,palette.color[key])</script>
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<input autocomplete="off" class="md-toggle" data-md-toggle="drawer" id="__drawer" type="checkbox"/>
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<input autocomplete="off" class="md-toggle" data-md-toggle="search" id="__search" type="checkbox"/>
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<label class="md-overlay" for="__drawer"></label>
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<div data-md-component="skip">
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<a class="md-skip" href="#dma-channels">
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Skip to content
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</a>
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</div>
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<div data-md-component="announce">
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</div>
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<header class="md-header" data-md-component="header">
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<nav aria-label="Header" class="md-header__inner md-grid">
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<a aria-label="PlayStation Specifications - psx-spx" class="md-header__button md-logo" data-md-component="logo" href=".." title="PlayStation Specifications - psx-spx">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M12 8a3 3 0 0 0 3-3 3 3 0 0 0-3-3 3 3 0 0 0-3 3 3 3 0 0 0 3 3m0 3.54C9.64 9.35 6.5 8 3 8v11c3.5 0 6.64 1.35 9 3.54 2.36-2.19 5.5-3.54 9-3.54V8c-3.5 0-6.64 1.35-9 3.54z"></path></svg>
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</a>
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<label class="md-header__button md-icon" for="__drawer">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M3 6h18v2H3V6m0 5h18v2H3v-2m0 5h18v2H3v-2z"></path></svg>
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</label>
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<div class="md-header__title" data-md-component="header-title">
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<div class="md-header__ellipsis">
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<div class="md-header__topic">
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<span class="md-ellipsis">
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PlayStation Specifications - psx-spx
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</span>
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</div>
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<div class="md-header__topic" data-md-component="header-topic">
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<span class="md-ellipsis">
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DMA Channels
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</span>
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</div>
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</div>
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</div>
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<form class="md-header__option" data-md-component="palette">
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<input class="md-option" data-md-color-accent="indigo" data-md-color-media="(prefers-color-scheme: light)" data-md-color-primary="indigo" data-md-color-scheme="default" id="__palette_1" name="__palette" type="radio"/>
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<label class="md-header__button md-icon" for="__palette_2" hidden="" title="Switch to dark mode">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M7 10a2 2 0 0 1 2 2 2 2 0 0 1-2 2 2 2 0 0 1-2-2 2 2 0 0 1 2-2m10-3a5 5 0 0 1 5 5 5 5 0 0 1-5 5H7a5 5 0 0 1-5-5 5 5 0 0 1 5-5h10M7 9a3 3 0 0 0-3 3 3 3 0 0 0 3 3h10a3 3 0 0 0 3-3 3 3 0 0 0-3-3H7z"></path></svg>
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</label>
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<input class="md-option" data-md-color-accent="blue" data-md-color-media="(prefers-color-scheme: dark)" data-md-color-primary="blue" data-md-color-scheme="slate" id="__palette_2" name="__palette" type="radio"/>
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<label class="md-header__button md-icon" for="__palette_1" hidden="" title="Switch to light mode">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M17 7H7a5 5 0 0 0-5 5 5 5 0 0 0 5 5h10a5 5 0 0 0 5-5 5 5 0 0 0-5-5m0 8a3 3 0 0 1-3-3 3 3 0 0 1 3-3 3 3 0 0 1 3 3 3 3 0 0 1-3 3z"></path></svg>
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</label>
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</form>
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<label class="md-header__button md-icon" for="__search">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M9.5 3A6.5 6.5 0 0 1 16 9.5c0 1.61-.59 3.09-1.56 4.23l.27.27h.79l5 5-1.5 1.5-5-5v-.79l-.27-.27A6.516 6.516 0 0 1 9.5 16 6.5 6.5 0 0 1 3 9.5 6.5 6.5 0 0 1 9.5 3m0 2C7 5 5 7 5 9.5S7 14 9.5 14 14 12 14 9.5 12 5 9.5 5z"></path></svg>
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</label>
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<div class="md-search" data-md-component="search" role="dialog">
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<label class="md-search__overlay" for="__search"></label>
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<div class="md-search__inner" role="search">
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<form class="md-search__form" name="search">
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<input aria-label="Search" autocapitalize="off" autocomplete="off" autocorrect="off" class="md-search__input" data-md-component="search-query" data-md-state="active" name="query" placeholder="Search" required="" spellcheck="false" type="text"/>
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<label class="md-search__icon md-icon" for="__search">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M9.5 3A6.5 6.5 0 0 1 16 9.5c0 1.61-.59 3.09-1.56 4.23l.27.27h.79l5 5-1.5 1.5-5-5v-.79l-.27-.27A6.516 6.516 0 0 1 9.5 16 6.5 6.5 0 0 1 3 9.5 6.5 6.5 0 0 1 9.5 3m0 2C7 5 5 7 5 9.5S7 14 9.5 14 14 12 14 9.5 12 5 9.5 5z"></path></svg>
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20 11v2H8l5.5 5.5-1.42 1.42L4.16 12l7.92-7.92L13.5 5.5 8 11h12z"></path></svg>
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</label>
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<button aria-label="Clear" class="md-search__icon md-icon" tabindex="-1" type="reset">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M19 6.41 17.59 5 12 10.59 6.41 5 5 6.41 10.59 12 5 17.59 6.41 19 12 13.41 17.59 19 19 17.59 13.41 12 19 6.41z"></path></svg>
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</button>
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</form>
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<div class="md-search__output">
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<div class="md-search__scrollwrap" data-md-scrollfix="">
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<div class="md-search-result" data-md-component="search-result">
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<div class="md-search-result__meta">
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Initializing search
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</div>
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<ol class="md-search-result__list"></ol>
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</div>
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</div>
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</div>
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</div>
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</div>
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<div class="md-header__source">
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<a class="md-source" data-md-component="source" href="https://github.com/psx-spx/psx-spx.github.io/" title="Go to repository">
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<div class="md-source__icon md-icon">
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<svg viewbox="0 0 448 512" xmlns="http://www.w3.org/2000/svg"><path d="M439.55 236.05 244 40.45a28.87 28.87 0 0 0-40.81 0l-40.66 40.63 51.52 51.52c27.06-9.14 52.68 16.77 43.39 43.68l49.66 49.66c34.23-11.8 61.18 31 35.47 56.69-26.49 26.49-70.21-2.87-56-37.34L240.22 199v121.85c25.3 12.54 22.26 41.85 9.08 55a34.34 34.34 0 0 1-48.55 0c-17.57-17.6-11.07-46.91 11.25-56v-123c-20.8-8.51-24.6-30.74-18.64-45L142.57 101 8.45 235.14a28.86 28.86 0 0 0 0 40.81l195.61 195.6a28.86 28.86 0 0 0 40.8 0l194.69-194.69a28.86 28.86 0 0 0 0-40.81z"></path></svg>
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</div>
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<div class="md-source__repository">
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GitHub
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</div>
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</a>
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</div>
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</nav>
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</header>
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<div class="md-container" data-md-component="container">
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<main class="md-main" data-md-component="main">
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<div class="md-main__inner md-grid">
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<div class="md-sidebar md-sidebar--primary" data-md-component="sidebar" data-md-type="navigation">
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<div class="md-sidebar__scrollwrap">
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<div class="md-sidebar__inner">
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<nav aria-label="Navigation" class="md-nav md-nav--primary" data-md-level="0">
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<label class="md-nav__title" for="__drawer">
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<a aria-label="PlayStation Specifications - psx-spx" class="md-nav__button md-logo" data-md-component="logo" href=".." title="PlayStation Specifications - psx-spx">
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M12 8a3 3 0 0 0 3-3 3 3 0 0 0-3-3 3 3 0 0 0-3 3 3 3 0 0 0 3 3m0 3.54C9.64 9.35 6.5 8 3 8v11c3.5 0 6.64 1.35 9 3.54 2.36-2.19 5.5-3.54 9-3.54V8c-3.5 0-6.64 1.35-9 3.54z"></path></svg>
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</a>
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PlayStation Specifications - psx-spx
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</label>
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<div class="md-nav__source">
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<a class="md-source" data-md-component="source" href="https://github.com/psx-spx/psx-spx.github.io/" title="Go to repository">
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<div class="md-source__icon md-icon">
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<svg viewbox="0 0 448 512" xmlns="http://www.w3.org/2000/svg"><path d="M439.55 236.05 244 40.45a28.87 28.87 0 0 0-40.81 0l-40.66 40.63 51.52 51.52c27.06-9.14 52.68 16.77 43.39 43.68l49.66 49.66c34.23-11.8 61.18 31 35.47 56.69-26.49 26.49-70.21-2.87-56-37.34L240.22 199v121.85c25.3 12.54 22.26 41.85 9.08 55a34.34 34.34 0 0 1-48.55 0c-17.57-17.6-11.07-46.91 11.25-56v-123c-20.8-8.51-24.6-30.74-18.64-45L142.57 101 8.45 235.14a28.86 28.86 0 0 0 0 40.81l195.61 195.6a28.86 28.86 0 0 0 40.8 0l194.69-194.69a28.86 28.86 0 0 0 0-40.81z"></path></svg>
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</div>
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<div class="md-source__repository">
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GitHub
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</div>
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</a>
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</div>
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<ul class="md-nav__list" data-md-scrollfix="">
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<li class="md-nav__item">
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<a class="md-nav__link" href="..">
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Home
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../memorymap/">
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Memory Map
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../iomap/">
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I/O Map
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../graphicsprocessingunitgpu/">
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Graphics Processing Unit (GPU)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../geometrytransformationenginegte/">
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Geometry Transformation Engine (GTE)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../macroblockdecodermdec/">
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Macroblock Decoder (MDEC)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../soundprocessingunitspu/">
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Sound Processing Unit (SPU)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../interrupts/">
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Interrupts
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</a>
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</li>
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<li class="md-nav__item md-nav__item--active">
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<input class="md-nav__toggle md-toggle" data-md-toggle="toc" id="__toc" type="checkbox"/>
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<label class="md-nav__link md-nav__link--active" for="__toc">
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DMA Channels
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<span class="md-nav__icon md-icon"></span>
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</label>
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<a class="md-nav__link md-nav__link--active" href="./">
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DMA Channels
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</a>
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<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
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<label class="md-nav__title" for="__toc">
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<span class="md-nav__icon md-icon"></span>
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Table of contents
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</label>
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<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
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<li class="md-nav__item">
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<a class="md-nav__link" href="#dma-register-summary">
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DMA Register Summary
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f801080hn10h-d_madr-dma-base-address-channel-06-rw">
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1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f801084hn10h-d_bcr-dma-block-control-channel-06-rw">
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1F801084h+N*10h - D#_BCR - DMA Block Control (Channel 0..6) (R/W)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f801088hn10h-d_chcr-dma-channel-control-channel-06-rw">
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1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f8010f0h-dpcr-dma-control-register-rw">
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1F8010F0h - DPCR - DMA Control Register (R/W)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f8010f4h-dicr-dma-interrupt-register-rw">
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1F8010F4h - DICR - DMA Interrupt Register (R/W)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f8010f8h-usually-7ffac68bh-or-0bfac688h">
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1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#1f8010fch-usually-00fffff7h-maybe-otc-fill-value">
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1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#commonly-used-dma-control-register-values-for-starting-dma-transfers">
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Commonly used DMA Control Register values for starting DMA transfers
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#dma-transfer-rates">
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DMA Transfer Rates
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</a>
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</li>
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||
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<li class="md-nav__item">
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<a class="md-nav__link" href="#dram-hyper-page-mode">
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DRAM Hyper Page mode
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="#cpu-operation-during-dma">
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CPU Operation during DMA
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</a>
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</li>
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</ul>
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</nav>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../timers/">
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Timers
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</a>
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</li>
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<li class="md-nav__item">
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||
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<a class="md-nav__link" href="../cdromdrive/">
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CDROM Drive
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../controllersandmemorycards/">
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Controllers and Memory Cards
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</a>
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||
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../pocketstation/">
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Pocketstation
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</a>
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../serialportsio/">
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Serial Port (SIO)
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</a>
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</li>
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<li class="md-nav__item">
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||
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<a class="md-nav__link" href="../expansionportpio/">
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Expansion Port (PIO)
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</a>
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||
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../memorycontrol/">
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Memory Control
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</a>
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||
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</li>
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<li class="md-nav__item">
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<a class="md-nav__link" href="../unpredictablethings/">
|
||
|
Unpredictable Things
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../cpuspecifications/">
|
||
|
CPU Specifications
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../kernelbios/">
|
||
|
Kernel (BIOS)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../arcadecabinets/">
|
||
|
Arcade Cabinets
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../cheatdevices/">
|
||
|
Cheat Devices
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||
|
PSX Dev-Board Chipsets
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../hardwarenumbers/">
|
||
|
Hardware Numbers
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../pinouts/">
|
||
|
Pinouts
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../aboutcredits/">
|
||
|
About & Credits
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||
|
CDROM Video CDs (VCD)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||
|
CDROM Internal Info on PSX CDROM Controller
|
||
|
</a>
|
||
|
</li>
|
||
|
</ul>
|
||
|
</nav>
|
||
|
</div>
|
||
|
</div>
|
||
|
</div>
|
||
|
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||
|
<div class="md-sidebar__scrollwrap">
|
||
|
<div class="md-sidebar__inner">
|
||
|
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||
|
<label class="md-nav__title" for="__toc">
|
||
|
<span class="md-nav__icon md-icon"></span>
|
||
|
Table of contents
|
||
|
</label>
|
||
|
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#dma-register-summary">
|
||
|
DMA Register Summary
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f801080hn10h-d_madr-dma-base-address-channel-06-rw">
|
||
|
1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f801084hn10h-d_bcr-dma-block-control-channel-06-rw">
|
||
|
1F801084h+N*10h - D#_BCR - DMA Block Control (Channel 0..6) (R/W)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f801088hn10h-d_chcr-dma-channel-control-channel-06-rw">
|
||
|
1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f8010f0h-dpcr-dma-control-register-rw">
|
||
|
1F8010F0h - DPCR - DMA Control Register (R/W)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f8010f4h-dicr-dma-interrupt-register-rw">
|
||
|
1F8010F4h - DICR - DMA Interrupt Register (R/W)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f8010f8h-usually-7ffac68bh-or-0bfac688h">
|
||
|
1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#1f8010fch-usually-00fffff7h-maybe-otc-fill-value">
|
||
|
1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#commonly-used-dma-control-register-values-for-starting-dma-transfers">
|
||
|
Commonly used DMA Control Register values for starting DMA transfers
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#dma-transfer-rates">
|
||
|
DMA Transfer Rates
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#dram-hyper-page-mode">
|
||
|
DRAM Hyper Page mode
|
||
|
</a>
|
||
|
</li>
|
||
|
<li class="md-nav__item">
|
||
|
<a class="md-nav__link" href="#cpu-operation-during-dma">
|
||
|
CPU Operation during DMA
|
||
|
</a>
|
||
|
</li>
|
||
|
</ul>
|
||
|
</nav>
|
||
|
</div>
|
||
|
</div>
|
||
|
</div>
|
||
|
<div class="md-content" data-md-component="content">
|
||
|
<article class="md-content__inner md-typeset">
|
||
|
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/dmachannels.md" title="Edit this page">
|
||
|
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||
|
</a>
|
||
|
<h1 id="dma-channels">DMA Channels</h1>
|
||
|
<h4 id="dma-register-summary">DMA Register Summary</h4>
|
||
|
<pre><code> 1F80108xh DMA0 channel 0 MDECin (RAM to MDEC)
|
||
|
1F80109xh DMA1 channel 1 MDECout (MDEC to RAM)
|
||
|
1F8010Axh DMA2 channel 2 GPU (lists + image data)
|
||
|
1F8010Bxh DMA3 channel 3 CDROM (CDROM to RAM)
|
||
|
1F8010Cxh DMA4 channel 4 SPU
|
||
|
1F8010Dxh DMA5 channel 5 PIO (Expansion Port)
|
||
|
1F8010Exh DMA6 channel 6 OTC (reverse clear OT) (GPU related)
|
||
|
1F8010F0h DPCR - DMA Control register
|
||
|
1F8010F4h DICR - DMA Interrupt register
|
||
|
</code></pre>
|
||
|
<p>These ports control DMA at the CPU-side. In most cases, you'll additionally
|
||
|
need to initialize an address (and transfer direction, transfer enabled, etc.)
|
||
|
at the remote-side (eg. at the GPU-side for DMA2).<br/></p>
|
||
|
<h4 id="1f801080hn10h-d_madr-dma-base-address-channel-06-rw">1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)</h4>
|
||
|
<pre><code> 0-23 Memory Address where the DMA will start reading from/writing to
|
||
|
24-31 Not used (always zero)
|
||
|
</code></pre>
|
||
|
<p>In SyncMode=0, the hardware doesn't update the MADR registers (it will contain
|
||
|
the start address even during and after the transfer) (unless Chopping is
|
||
|
enabled, in that case it does update MADR, same does probably also happen when
|
||
|
getting interrupted by a higher priority DMA channel).<br/>
|
||
|
In SyncMode=1 and SyncMode=2, the hardware does update MADR (it will contain
|
||
|
the start address of the currently transferred block; at transfer end, it'll
|
||
|
hold the end-address in SyncMode=1, or the 00FFFFFFh end-code in SyncMode=2)<br/>
|
||
|
Note: Address bit0-1 are writeable, but any updated current/end addresses are
|
||
|
word-aligned with bit0-1 forced to zero.<br/></p>
|
||
|
<h4 id="1f801084hn10h-d_bcr-dma-block-control-channel-06-rw">1F801084h+N*10h - D#_BCR - DMA Block Control (Channel 0..6) (R/W)</h4>
|
||
|
<p>For SyncMode=0 (ie. for OTC and CDROM):<br/></p>
|
||
|
<pre><code> 0-15 BC Number of words (0001h..FFFFh) (or 0=10000h words)
|
||
|
16-31 0 Not used (usually 0 for OTC, or 1 ("one block") for CDROM)
|
||
|
</code></pre>
|
||
|
<p>For SyncMode=1 (ie. for MDEC, SPU, and GPU-vram-data):<br/></p>
|
||
|
<pre><code> 0-15 BS Blocksize (words) ;for GPU/SPU max 10h, for MDEC max 20h
|
||
|
16-31 BA Amount of blocks ;ie. total length = BS*BA words
|
||
|
</code></pre>
|
||
|
<p>For SyncMode=2 (ie. for GPU-command-lists):<br/></p>
|
||
|
<pre><code> 0-31 0 Not used (should be zero) (transfer ends at END-CODE in list)
|
||
|
</code></pre>
|
||
|
<p>BC/BS/BA can be in range 0001h..FFFFh (or 0=10000h). For BS, take care not to
|
||
|
set the blocksize larger than the buffer of the corresponding unit can hold.
|
||
|
(GPU and SPU both have a 16-word buffer). A larger blocksize means faster
|
||
|
transfer.<br/>
|
||
|
SyncMode=1 decrements BA to zero, SyncMode=0 with chopping enabled decrements
|
||
|
BC to zero (aside from that two cases, D#_BCR isn't changed during/after
|
||
|
transfer).<br/></p>
|
||
|
<h4 id="1f801088hn10h-d_chcr-dma-channel-control-channel-06-rw">1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)</h4>
|
||
|
<pre><code> 0 Transfer Direction (0=To Main RAM, 1=From Main RAM)
|
||
|
1 Memory Address Step (0=Forward;+4, 1=Backward;-4)
|
||
|
2-7 Not used (always zero)
|
||
|
8 Chopping Enable (0=Normal, 1=Chopping; run CPU during DMA gaps)
|
||
|
9-10 SyncMode, Transfer Synchronisation/Mode (0-3):
|
||
|
0 Start immediately and transfer all at once (used for CDROM, OTC)
|
||
|
1 Sync blocks to DMA requests (used for MDEC, SPU, and GPU-data)
|
||
|
2 Linked-List mode (used for GPU-command-lists)
|
||
|
3 Reserved (not used)
|
||
|
11-15 Not used (always zero)
|
||
|
16-18 Chopping DMA Window Size (1 SHL N words)
|
||
|
19 Not used (always zero)
|
||
|
20-22 Chopping CPU Window Size (1 SHL N clks)
|
||
|
23 Not used (always zero)
|
||
|
24 Start/Busy (0=Stopped/Completed, 1=Start/Enable/Busy)
|
||
|
25-27 Not used (always zero)
|
||
|
28 Start/Trigger (0=Normal, 1=Manual Start; use for SyncMode=0)
|
||
|
29 Unknown (R/W) Pause? (0=No, 1=Pause?) (For SyncMode=0 only?)
|
||
|
30 Unknown (R/W)
|
||
|
31 Not used (always zero)
|
||
|
</code></pre>
|
||
|
<p>The Start/Trigger bit is automatically cleared upon BEGIN of the transfer, this
|
||
|
bit needs to be set only in SyncMode=0 (setting it in other SyncModes would
|
||
|
force the first block to be transferred instantly without DRQ, which isn't
|
||
|
desired).<br/>
|
||
|
The Start/Busy bit is automatically cleared upon COMPLETION of the transfer,
|
||
|
this bit must be always set for all SyncModes when starting a transfer.<br/>
|
||
|
For DMA6/OTC there are some restrictions, D6_CHCR has only three
|
||
|
read/write-able bits: Bit24,28,30. All other bits are read-only: Bit1 is always
|
||
|
1 (step=backward), and the other bits are always 0.<br/></p>
|
||
|
<h4 id="1f8010f0h-dpcr-dma-control-register-rw">1F8010F0h - DPCR - DMA Control Register (R/W)</h4>
|
||
|
<pre><code> 0-2 DMA0, MDECin Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
3 DMA0, MDECin Master Enable (0=Disable, 1=Enable)
|
||
|
4-6 DMA1, MDECout Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
7 DMA1, MDECout Master Enable (0=Disable, 1=Enable)
|
||
|
8-10 DMA2, GPU Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
11 DMA2, GPU Master Enable (0=Disable, 1=Enable)
|
||
|
12-14 DMA3, CDROM Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
15 DMA3, CDROM Master Enable (0=Disable, 1=Enable)
|
||
|
16-18 DMA4, SPU Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
19 DMA4, SPU Master Enable (0=Disable, 1=Enable)
|
||
|
20-22 DMA5, PIO Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
23 DMA5, PIO Master Enable (0=Disable, 1=Enable)
|
||
|
24-26 DMA6, OTC Priority (0..7; 0=Highest, 7=Lowest)
|
||
|
27 DMA6, OTC Master Enable (0=Disable, 1=Enable)
|
||
|
28-30 Unknown, Priority Offset or so? (R/W)
|
||
|
31 Unknown, no effect? (R/W)
|
||
|
</code></pre>
|
||
|
<p>Initial value on reset is 07654321h. If two or more channels have the same
|
||
|
priority setting, then the priority is determined by the channel number
|
||
|
(DMA0=Lowest, DMA6=Highest).<br/></p>
|
||
|
<h4 id="1f8010f4h-dicr-dma-interrupt-register-rw">1F8010F4h - DICR - DMA Interrupt Register (R/W)</h4>
|
||
|
<pre><code> 0-5 Unknown (read/write-able)
|
||
|
6-14 Not used (always zero)
|
||
|
15 Force IRQ (sets bit31) (0=None, 1=Force Bit31=1)
|
||
|
16-22 IRQ Enable for DMA0..DMA6 (0=None, 1=Enable)
|
||
|
23 IRQ Master Enable for DMA0..DMA6 (0=None, 1=Enable)
|
||
|
24-30 IRQ Flags for DMA0..DMA6 (0=None, 1=IRQ) (Write 1 to reset)
|
||
|
31 IRQ Master Flag (0=None, 1=IRQ) (Read only)
|
||
|
</code></pre>
|
||
|
<p>IRQ flags in Bit(24+n) are set upon DMAn completion - but caution - they are
|
||
|
set ONLY if enabled in Bit(16+n).<br/>
|
||
|
Bit31 is a simple readonly flag that follows the following rules:<br/></p>
|
||
|
<pre><code> IF b15=1 OR (b23=1 AND (b16-22 AND b24-30)>0) THEN b31=1 ELSE b31=0
|
||
|
</code></pre>
|
||
|
<p>Upon 0-to-1 transition of Bit31, the IRQ3 flag (in Port 1F801070h) gets set.<br/>
|
||
|
Bit24-30 are acknowledged (reset to zero) when writing a "1" to that bits (and,
|
||
|
additionally, IRQ3 must be acknowledged via Port 1F801070h).<br/></p>
|
||
|
<h4 id="1f8010f8h-usually-7ffac68bh-or-0bfac688h">1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)</h4>
|
||
|
<pre><code> (changes to 7FE358D1h after DMA transfer)
|
||
|
</code></pre>
|
||
|
<h4 id="1f8010fch-usually-00fffff7h-maybe-otc-fill-value">1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)</h4>
|
||
|
<pre><code> (stays so even after DMA transfer)
|
||
|
</code></pre>
|
||
|
<p>Contains strange read-only values (but not the usual "Garbage").<br/>
|
||
|
Not yet tested during transfer, might be remaining length and address?<br/></p>
|
||
|
<h4 id="commonly-used-dma-control-register-values-for-starting-dma-transfers">Commonly used DMA Control Register values for starting DMA transfers</h4>
|
||
|
<pre><code> DMA0 MDEC.IN 01000201h (always)
|
||
|
DMA1 MDEC.OUT 01000200h (always)
|
||
|
DMA2 GPU 01000200h (VramRead), 01000201h (VramWrite), 01000401h (List)
|
||
|
DMA3 CDROM 11000000h (normal), 11400100h (chopped, rarely used)
|
||
|
DMA4 SPU 01000201h (write), 01000200h (read, rarely used)
|
||
|
DMA5 PIO N/A (not used by any known games)
|
||
|
DMA6 OTC 11000002h (always)
|
||
|
</code></pre>
|
||
|
<p>XXX: DMA2 values 01000201h (VramWrite), 01000401h (List) aren't 100% confirmed
|
||
|
to be used by ALL existing games. All other values are always used as listed
|
||
|
above.<br/></p>
|
||
|
<h4 id="dma-transfer-rates">DMA Transfer Rates</h4>
|
||
|
<pre><code> DMA0 MDEC.IN 1 clk/word ;0110h clks per 100h words ;\plus whatever
|
||
|
DMA1 MDEC.OUT 1 clk/word ;0110h clks per 100h words ;/decompression time
|
||
|
DMA2 GPU 1 clk/word ;0110h clks per 100h words ;-plus ...
|
||
|
DMA3 CDROM/BIOS 24 clks/word ;1800h clks per 100h words ;\plus single/double
|
||
|
DMA3 CDROM/GAMES 40 clks/word ;2800h clks per 100h words ;/speed sector rate
|
||
|
DMA4 SPU 4 clks/word ;0420h clks per 100h words ;-plus ...
|
||
|
DMA5 PIO 20 clks/word ;1400h clks per 100h words ;-not actually used
|
||
|
DMA6 OTC 1 clk/word ;0110h clks per 100h words ;-plus nothing
|
||
|
</code></pre>
|
||
|
<p>MDEC decompression time is still unknown (may vary on RLE and color/mono).<br/>
|
||
|
GPU polygon rendering time is unknown (may be quite slow for large polys).<br/>
|
||
|
GPU vram read/write time is unknown (may vary on horizontal screen resolution).<br/>
|
||
|
CDROM BIOS default is 24 clks, for some reason most games change it to 40 clks.<br/>
|
||
|
SPU transfer is unknown (may have some extra delays).<br/>
|
||
|
XXX is SPU really only 4 clks (theoretically SPU access should be slower)?<br/>
|
||
|
PIO isn't used by any games (and if used: could be configured to other rates)<br/>
|
||
|
OTC is just writing to RAM without extra overload.<br/>
|
||
|
CDROM/SPU/PIO timings can be configured via Memory Control registers.<br/></p>
|
||
|
<h4 id="dram-hyper-page-mode">DRAM Hyper Page mode</h4>
|
||
|
<p>DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock
|
||
|
cycle per word (effectively around 17 clks per 16 words, due to required row
|
||
|
address loading, probably plus some further minimal overload due to refresh
|
||
|
cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM
|
||
|
access takes 1 opcode cycle plus 6 waitstates, ie. 7 cycles in total)<br/></p>
|
||
|
<h4 id="cpu-operation-during-dma">CPU Operation during DMA</h4>
|
||
|
<p>Basically, the CPU is stopped during DMA (theoretically, the CPU could be kept
|
||
|
running when accessing only cache, scratchpad and on-chip I/O ports like DMA
|
||
|
registers, and during the CDROM/SPU/PIO waitstates it could even access Main
|
||
|
RAM, but these situations aren't supported).<br/>
|
||
|
However, the CPU operation resumes during periods when DMA gets interrupted
|
||
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(ie. after SyncMode 1 blocks, after SyncMode 2 list entries) (or in SyncMode 0
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with Chopping enabled).<br/></p>
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M4 11v2h12l-5.5 5.5 1.42 1.42L19.84 12l-7.92-7.92L10.5 5.5 16 11H4z"></path></svg>
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</nav>
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