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Unpredictable Things
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CPU Specifications
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||||
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||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../kernelbios/">
|
||||
Kernel (BIOS)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../arcadecabinets/">
|
||||
Arcade Cabinets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cheatdevices/">
|
||||
Cheat Devices
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item md-nav__item--active">
|
||||
<input class="md-nav__toggle md-toggle" data-md-toggle="toc" id="__toc" type="checkbox"/>
|
||||
<label class="md-nav__link md-nav__link--active" for="__toc">
|
||||
About & Credits
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
</label>
|
||||
<a class="md-nav__link md-nav__link--active" href="./">
|
||||
About & Credits
|
||||
</a>
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#credits">
|
||||
Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psxspx-homepage">
|
||||
PSXSPX homepage
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#contact">
|
||||
Contact
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#index">
|
||||
Index
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#credits">
|
||||
Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psxspx-homepage">
|
||||
PSXSPX homepage
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#contact">
|
||||
Contact
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#index">
|
||||
Index
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/aboutcredits.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="about-credits">About & Credits</h1>
|
||||
<h4 id="credits">Credits</h4>
|
||||
<p>GPU.TXT by doomed/padua; based on info from K-communications &
|
||||
Nagra/Blackbag<br/>
|
||||
GTE.TXT by doomed@c64.org / psx.rules.org<br/>
|
||||
SPU.TXT by doomed@c64.org / psx.rules.org<br/>
|
||||
CDINFO.TXT by doomed with big thanks to Barubary, who rewrote a large part<br/>
|
||||
SYSTEM.TXT by doomed with thanx to Herozero for breakpoint info<br/>
|
||||
PS_ENG.TXT PlayStation PAD/Memory Interface Protocol by HFB03536<br/>
|
||||
IDT79R3041 Hardware User's Manual by Integrated Device Technology, Inc.<br/>
|
||||
IDTR3051, R3052 RISController User's Manual by Integrated Device Technology<br/>
|
||||
PSX.* by Joshua Walker (additional details in various distorted file formats)<br/>
|
||||
LIBMIRAGE by Rok; info/source code for various cdrom-image formats<br/>
|
||||
psxdev.ru; cdrom sub-cpu decapping<br/></p>
|
||||
<h4 id="psxspx-homepage">PSXSPX homepage</h4>
|
||||
<p>http://problemkaputt.de/psx.htm no$psx emulator/debugger<br/>
|
||||
http://problemkaputt.de/psx-spx.htm psx specs in html formal<br/>
|
||||
http://problemkaputt.de/psx-spx.txt psx specs in text formal<br/></p>
|
||||
<h4 id="contact">Contact</h4>
|
||||
<p>http://problemkaputt.de/email.htm (spam-shielded)<br/></p>
|
||||
<h2 id="index">Index</h2>
|
||||
<p><a href="#contents">Contents</a><br/>
|
||||
<a href="../memorymap/">Memory Map</a><br/>
|
||||
<a href="../iomap/">I/O Map</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/">Graphics Processing Unit (GPU)</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-io-ports-dma-channels-commands-vram">GPU I/O Ports, DMA Channels, Commands, VRAM</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-render-polygon-commands">GPU Render Polygon Commands</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-render-line-commands">GPU Render Line Commands</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-render-rectangle-commands">GPU Render Rectangle Commands</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-rendering-attributes">GPU Rendering Attributes</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-memory-transfer-commands">GPU Memory Transfer Commands</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-other-commands">GPU Other Commands</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-display-control-commands-gp1">GPU Display Control Commands (GP1)</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-status-register">GPU Status Register</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-versions">GPU Versions</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-depth-ordering">GPU Depth Ordering</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-video-memory-vram">GPU Video Memory (VRAM)</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-texture-caching">GPU Texture Caching</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-timings">GPU Timings</a><br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-misc">GPU (MISC)</a><br/>
|
||||
<a href="../geometrytransformationenginegte/">Geometry Transformation Engine (GTE)</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-overview">GTE Overview</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-registers">GTE Registers</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-saturation">GTE Saturation</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-opcode-summary">GTE Opcode Summary</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-coordinate-calculation-commands">GTE Coordinate Calculation Commands</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-general-purpose-calculation-commands">GTE General Purpose Calculation Commands</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-color-calculation-commands">GTE Color Calculation Commands</a><br/>
|
||||
<a href="../geometrytransformationenginegte/#gte-division-inaccuracy">GTE Division Inaccuracy</a><br/>
|
||||
<a href="../macroblockdecodermdec/">Macroblock Decoder (MDEC)</a><br/>
|
||||
<a href="../macroblockdecodermdec/#mdec-io-ports">MDEC I/O Ports</a><br/>
|
||||
<a href="../macroblockdecodermdec/#mdec-commands">MDEC Commands</a><br/>
|
||||
<a href="../macroblockdecodermdec/#mdec-decompression">MDEC Decompression</a><br/>
|
||||
<a href="../macroblockdecodermdec/#mdec-data-format">MDEC Data Format</a><br/>
|
||||
<a href="../soundprocessingunitspu/">Sound Processing Unit (SPU)</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-overview">SPU Overview</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-adpcm-samples">SPU ADPCM Samples</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-adpcm-pitch">SPU ADPCM Pitch</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-volume-and-adsr-generator">SPU Volume and ADSR Generator</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-voice-flags">SPU Voice Flags</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-noise-generator">SPU Noise Generator</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-control-and-status-register">SPU Control and Status Register</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-memory-access">SPU Memory Access</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-interrupt">SPU Interrupt</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-reverb-registers">SPU Reverb Registers</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-reverb-formula">SPU Reverb Formula</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-reverb-examples">SPU Reverb Examples</a><br/>
|
||||
<a href="../soundprocessingunitspu/#spu-unknown-registers">SPU Unknown Registers</a><br/>
|
||||
<a href="../interrupts/">Interrupts</a><br/>
|
||||
<a href="../dmachannels/">DMA Channels</a><br/>
|
||||
<a href="../timers/">Timers</a><br/>
|
||||
<a href="../cdromdrive/">CDROM Drive</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-controller-io-ports">CDROM Controller I/O Ports</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-controller-command-summary">CDROM Controller Command Summary</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-control-commands">CDROM - Control Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-seek-commands">CDROM - Seek Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-read-commands">CDROM - Read Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-status-commands">CDROM - Status Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-cd-audio-commands">CDROM - CD Audio Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands">CDROM - Test Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands-version-switches-region-chipset-scex">CDROM - Test Commands - Version, Switches, Region, Chipset, SCEx</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands-test-drive-mechanics">CDROM - Test Commands - Test Drive Mechanics</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands-prototype-debug-transmission">CDROM - Test Commands - Prototype Debug Transmission</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands-readwrite-decoder-ram-and-io-ports">CDROM - Test Commands - Read/Write Decoder RAM and I/O Ports</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-test-commands-read-hc05-sub-cpu-ram-and-io-ports">CDROM - Test Commands - Read HC05 SUB-CPU RAM and I/O Ports</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-secret-unlock-commands">CDROM - Secret Unlock Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-video-cd-commands">CDROM - Video CD Commands</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-mainloopresponses">CDROM - Mainloop/Responses</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-response-timings">CDROM - Response Timings</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-responsedata-queueing">CDROM - Response/Data Queueing</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-format">CDROM Disk Format</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-subchannels">CDROM Subchannels</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-sector-encoding">CDROM Sector Encoding</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-xa-subheader-file-channel-interleave">CDROM XA Subheader, File, Channel, Interleave</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-xa-audio-adpcm-compression">CDROM XA Audio ADPCM Compression</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-iso-volume-descriptors">CDROM ISO Volume Descriptors</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-iso-file-and-directory-descriptors">CDROM ISO File and Directory Descriptors</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-iso-misc">CDROM ISO Misc</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-file-formats">CDROM File Formats</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-protection-scex-strings">CDROM Protection - SCEx Strings</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-protection-bypassing-it">CDROM Protection - Bypassing it</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-protection-modchips">CDROM Protection - Modchips</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-protection-chipless-modchips">CDROM Protection - Chipless Modchips</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-protection-libcrypt">CDROM Protection - LibCrypt</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-ccdimgsub-clonecd">CDROM Disk Images CCD/IMG/SUB (CloneCD)</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-cdi-discjuggler">CDROM Disk Images CDI (DiscJuggler)</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-cuebincdt-cdrwin">CDROM Disk Images CUE/BIN/CDT (Cdrwin)</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-mdsmdf-alcohol-120">CDROM Disk Images MDS/MDF (Alcohol 120%)</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-nrg-nero">CDROM Disk Images NRG (Nero)</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-imagecontainers-cdz">CDROM Disk Image/Containers CDZ</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-imagecontainers-ecm">CDROM Disk Image/Containers ECM</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-subchannel-images">CDROM Subchannel Images</a><br/>
|
||||
<a href="../cdromdrive/#cdrom-disk-images-other-formats">CDROM Disk Images Other Formats</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/">CDROM Internal Info on PSX CDROM Controller</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-instruction-set">CDROM Internal HC05 Instruction Set</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-on-chip-io-ports">CDROM Internal HC05 On-Chip I/O Ports</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-on-chip-io-ports-extras">CDROM Internal HC05 On-Chip I/O Ports - Extras</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-io-port-usage-in-psx">CDROM Internal HC05 I/O Port Usage in PSX</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-motorola-selftest-mode">CDROM Internal HC05 Motorola Selftest Mode</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-motorola-selftest-mode-52pin-chips">CDROM Internal HC05 Motorola Selftest Mode (52pin chips)</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-hc05-motorola-selftest-mode-80pin-chips">CDROM Internal HC05 Motorola Selftest Mode (80pin chips)</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-cxd1815q-sub-cpu-configuration-registers">CDROM Internal CXD1815Q Sub-CPU Configuration Registers</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-cxd1815q-sub-cpu-sector-status-registers">CDROM Internal CXD1815Q Sub-CPU Sector Status Registers</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-cxd1815q-sub-cpu-address-registers">CDROM Internal CXD1815Q Sub-CPU Address Registers</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-cxd1815q-sub-cpu-misc-registers">CDROM Internal CXD1815Q Sub-CPU Misc Registers</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cx0x3x-cxa1782br-servo-amplifier">CDROM Internal Commands CX(0x..3x) - CXA1782BR Servo Amplifier</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cx4xex-cxd2510q-signal-processor">CDROM Internal Commands CX(4x..Ex) - CXD2510Q Signal Processor</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cx0xex-cxd2545q-servosignal-combo">CDROM Internal Commands CX(0x..Ex) - CXD2545Q Servo/Signal Combo</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cx0xex-cxd2938q-servosignalspu-combo">CDROM Internal Commands CX(0x..Ex) - CXD2938Q Servo/Signal/SPU Combo</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cxxx-notes">CDROM Internal Commands CX(xx) - Notes</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-commands-cxxx-summary-of-used-cxxx-commands">CDROM Internal Commands CX(xx) - Summary of Used CX(xx) Commands</a><br/>
|
||||
<a href="../cdrominternalinfoonpsxcdromcontroller/#cdrom-internal-coefficients-for-cxd2545q">CDROM Internal Coefficients (for CXD2545Q)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/">CDROM Video CDs (VCD)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-iso-basic-files-info-entries-avseqnn-iso-filesystem">VCD ISO Basic Files (INFO, ENTRIES, AVSEQnn, ISO Filesystem)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-iso-playback-control-pbc-files-psd-lot-itemnnnn">VCD ISO Playback Control PBC Files (PSD, LOT, ITEMnnnn)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-iso-search-files-scandata-search-tracks-spicontx">VCD ISO Search Files (SCANDATA, SEARCH, TRACKS, SPICONTX)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-iso-misc-files-captnn-audionn-karinfo-pictures-cdi">VCD ISO Misc files (CAPTnn, AUDIOnn, KARINFO, PICTURES, CDI)</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-mpeg-1-multiplex-stream">VCD MPEG-1 Multiplex Stream</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-mpeg-1-video-stream">VCD MPEG-1 Video Stream</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#vcd-mp2-audio-stream">VCD MP2 Audio Stream</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#inflate">Inflate</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#inflate-core-functions">Inflate - Core Functions</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#inflate-initialization--tree-creation">Inflate - Initialization & Tree Creation</a><br/>
|
||||
<a href="../cdromvideocdsvcd/#inflate-headers-and-checksums">Inflate - Headers and Checksums</a><br/>
|
||||
<a href="../controllersandmemorycards/">Controllers and Memory Cards</a><br/>
|
||||
<a href="../controllersandmemorycards/#controller-and-memory-card-io-ports">Controller and Memory Card I/O Ports</a><br/>
|
||||
<a href="../controllersandmemorycards/#controller-and-memory-card-misc">Controller and Memory Card Misc</a><br/>
|
||||
<a href="../controllersandmemorycards/#controller-and-memory-card-signals">Controller and Memory Card Signals</a><br/>
|
||||
<a href="../controllersandmemorycards/#controller-and-memory-card-multitap-adaptor">Controller and Memory Card Multitap Adaptor</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-communication-sequence">Controllers - Communication Sequence</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-standard-digitalanalog-controllers">Controllers - Standard Digital/Analog Controllers</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-mouse">Controllers - Mouse</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-racing-controllers">Controllers - Racing Controllers</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-lightguns">Controllers - Lightguns</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-lightguns-namco-guncon">Controllers - Lightguns - Namco (GunCon)</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-lightguns-konami-justifierhyperblaster-irq10">Controllers - Lightguns - Konami Justifier/Hyperblaster (IRQ10)</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-lightguns-psx-lightgun-games">Controllers - Lightguns - PSX Lightgun Games</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-rumble-configuration">Controllers - Rumble Configuration</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-dance-mats">Controllers - Dance Mats</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-fishing-controllers">Controllers - Fishing Controllers</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-i-mode-adaptor-mobile-internet">Controllers - I-Mode Adaptor (Mobile Internet)</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-additional-inputs">Controllers - Additional Inputs</a><br/>
|
||||
<a href="../controllersandmemorycards/#controllers-misc">Controllers - Misc</a><br/>
|
||||
<a href="../controllersandmemorycards/#memory-card-readwrite-commands">Memory Card Read/Write Commands</a><br/>
|
||||
<a href="../controllersandmemorycards/#memory-card-data-format">Memory Card Data Format</a><br/>
|
||||
<a href="../controllersandmemorycards/#memory-card-images">Memory Card Images</a><br/>
|
||||
<a href="../controllersandmemorycards/#memory-card-notes">Memory Card Notes</a><br/>
|
||||
<a href="../pocketstation/">Pocketstation</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-overview">Pocketstation Overview</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-map">Pocketstation I/O Map</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-memory-map">Pocketstation Memory Map</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-video-and-audio">Pocketstation IO Video and Audio</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-interrupts-and-buttons">Pocketstation IO Interrupts and Buttons</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-timers-and-real-time-clock">Pocketstation IO Timers and Real-Time Clock</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-infrared">Pocketstation IO Infrared</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-memory-control">Pocketstation IO Memory-Control</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-communication-ports">Pocketstation IO Communication Ports</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-io-power-control">Pocketstation IO Power Control</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-function-summary">Pocketstation SWI Function Summary</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-misc-functions">Pocketstation SWI Misc Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-communication-functions">Pocketstation SWI Communication Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-execute-functions">Pocketstation SWI Execute Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-datetimealarm-functions">Pocketstation SWI Date/Time/Alarm Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-flash-functions">Pocketstation SWI Flash Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-swi-useless-functions">Pocketstation SWI Useless Functions</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-bu-command-summary">Pocketstation BU Command Summary</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-bu-standard-memory-card-commands">Pocketstation BU Standard Memory Card Commands</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-bu-basic-pocketstation-commands">Pocketstation BU Basic Pocketstation Commands</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-bu-custom-pocketstation-commands">Pocketstation BU Custom Pocketstation Commands</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-file-headericons">Pocketstation File Header/Icons</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-file-images">Pocketstation File Images</a><br/>
|
||||
<a href="../pocketstation/#pocketstation-xboo-cable">Pocketstation XBOO Cable</a><br/>
|
||||
<a href="../serialportsio/">Serial Port (SIO)</a><br/>
|
||||
<a href="../expansionportpio/">Expansion Port (PIO)</a><br/>
|
||||
<a href="../expansionportpio/#exp1-expansion-rom-header">EXP1 Expansion ROM Header</a><br/>
|
||||
<a href="../expansionportpio/#exp2-dual-serial-port-for-tty-debug-terminal">EXP2 Dual Serial Port (for TTY Debug Terminal)</a><br/>
|
||||
<a href="../expansionportpio/#exp2-dtl-h2000-io-ports">EXP2 DTL-H2000 I/O Ports</a><br/>
|
||||
<a href="../expansionportpio/#exp2-post-registers">EXP2 Post Registers</a><br/>
|
||||
<a href="../expansionportpio/#exp2-nocash-emulation-expansion">EXP2 Nocash Emulation Expansion</a><br/>
|
||||
<a href="../memorycontrol/">Memory Control</a><br/>
|
||||
<a href="../unpredictablethings/">Unpredictable Things</a><br/>
|
||||
<a href="../cpuspecifications/">CPU Specifications</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-registers">CPU Registers</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-opcode-encoding">CPU Opcode Encoding</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-loadstore-opcodes">CPU Load/Store Opcodes</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-alu-opcodes">CPU ALU Opcodes</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-jump-opcodes">CPU Jump Opcodes</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-coprocessor-opcodes">CPU Coprocessor Opcodes</a><br/>
|
||||
<a href="../cpuspecifications/#cpu-pseudo-opcodes">CPU Pseudo Opcodes</a><br/>
|
||||
<a href="../cpuspecifications/#cop0-register-summary">COP0 - Register Summary</a><br/>
|
||||
<a href="../cpuspecifications/#cop0-exception-handling">COP0 - Exception Handling</a><br/>
|
||||
<a href="../cpuspecifications/#cop0-misc">COP0 - Misc</a><br/>
|
||||
<a href="../cpuspecifications/#cop0-debug-registers">COP0 - Debug Registers</a><br/>
|
||||
<a href="../kernelbios/">Kernel (BIOS)</a><br/>
|
||||
<a href="../kernelbios/#bios-overview">BIOS Overview</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-map">BIOS Memory Map</a><br/>
|
||||
<a href="../kernelbios/#bios-function-summary">BIOS Function Summary</a><br/>
|
||||
<a href="../kernelbios/#bios-file-functions">BIOS File Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-file-execute-and-flush-cache">BIOS File Execute and Flush Cache</a><br/>
|
||||
<a href="../kernelbios/#bios-cdrom-functions">BIOS CDROM Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-card-functions">BIOS Memory Card Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-interruptexception-handling">BIOS Interrupt/Exception Handling</a><br/>
|
||||
<a href="../kernelbios/#bios-event-functions">BIOS Event Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-event-summary">BIOS Event Summary</a><br/>
|
||||
<a href="../kernelbios/#bios-thread-functions">BIOS Thread Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-timer-functions">BIOS Timer Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-joypad-functions">BIOS Joypad Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-gpu-functions">BIOS GPU Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-allocation">BIOS Memory Allocation</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-fillcopycompare-slow">BIOS Memory Fill/Copy/Compare (SLOW)</a><br/>
|
||||
<a href="../kernelbios/#bios-string-functions">BIOS String Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-numberstringcharacter-conversion">BIOS Number/String/Character Conversion</a><br/>
|
||||
<a href="../kernelbios/#bios-misc-functions">BIOS Misc Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-internal-boot-functions">BIOS Internal Boot Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-more-internal-functions">BIOS More Internal Functions</a><br/>
|
||||
<a href="../kernelbios/#bios-pc-file-server">BIOS PC File Server</a><br/>
|
||||
<a href="../kernelbios/#bios-tty-console-stdio">BIOS TTY Console (std_io)</a><br/>
|
||||
<a href="../kernelbios/#bios-character-sets">BIOS Character Sets</a><br/>
|
||||
<a href="../kernelbios/#bios-control-blocks">BIOS Control Blocks</a><br/>
|
||||
<a href="../kernelbios/#bios-versions">BIOS Versions</a><br/>
|
||||
<a href="../kernelbios/#bios-patches">BIOS Patches</a><br/>
|
||||
<a href="../arcadecabinets/">Arcade Cabinets</a><br/>
|
||||
<a href="../cheatdevices/">Cheat Devices</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-datel-io">Cheat Devices - Datel I/O</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-datel-db25-comms-link-protocol">Cheat Devices - Datel DB25 Comms Link Protocol</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-datel-chipset-pinouts">Cheat Devices - Datel Chipset Pinouts</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-datel-cheat-code-format">Cheat Devices - Datel Cheat Code Format</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-memory-and-io-map">Cheat Devices - Xplorer Memory and I/O Map</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-db25-parallel-port-function-summary">Cheat Devices - Xplorer DB25 Parallel Port Function Summary</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-db25-parallel-port-command-handler">Cheat Devices - Xplorer DB25 Parallel Port Command Handler</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-db25-parallel-port-low-level-transfer-protocol">Cheat Devices - Xplorer DB25 Parallel Port Low Level Transfer Protocol</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-versions">Cheat Devices - Xplorer Versions</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-chipset-pinouts">Cheat Devices - Xplorer Chipset Pinouts</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-cheat-code-format">Cheat Devices - Xplorer Cheat Code Format</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-xplorer-cheat-code-and-rom-image-decryption">Cheat Devices - Xplorer Cheat Code and ROM-Image Decryption</a><br/>
|
||||
<a href="../cheatdevices/#cheat-devices-flasheeproms">Cheat Devices - FLASH/EEPROMs</a><br/>
|
||||
<a href="../psxdevboardchipsets/">PSX Dev-Board Chipsets</a><br/>
|
||||
<a href="../hardwarenumbers/">Hardware Numbers</a><br/>
|
||||
<a href="../pinouts/">Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-controller-ports-and-memory-card-ports">Pinouts - Controller Ports and Memory-Card Ports</a><br/>
|
||||
<a href="../pinouts/#pinouts-audio-video-power-expansion-ports">Pinouts - Audio, Video, Power, Expansion Ports</a><br/>
|
||||
<a href="../pinouts/#pinouts-sio-pinouts">Pinouts - SIO Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-chipset-summary">Pinouts - Chipset Summary</a><br/>
|
||||
<a href="../pinouts/#pinouts-cpu-pinouts">Pinouts - CPU Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-gpu-pinouts-for-old-160-pin-gpu">Pinouts - GPU Pinouts (for old 160-pin GPU)</a><br/>
|
||||
<a href="../pinouts/#pinouts-gpu-pinouts-for-new-208-pin-gpu">Pinouts - GPU Pinouts (for new 208-pin GPU)</a><br/>
|
||||
<a href="../pinouts/#pinouts-spu-pinouts">Pinouts - SPU Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-drv-pinouts">Pinouts - DRV Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-vcd-pinouts">Pinouts - VCD Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-hc05-pinouts">Pinouts - HC05 Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-mem-pinouts">Pinouts - MEM Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-clk-pinouts">Pinouts - CLK Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-pwr-pinouts">Pinouts - PWR Pinouts</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-digital-joypad-scph-1080">Pinouts - Component List and Chipset Pin-Outs for Digital Joypad, SCPH-1080</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-analog-joypad-scph-1150">Pinouts - Component List and Chipset Pin-Outs for Analog Joypad, SCPH-1150</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-analog-joypad-scph-1200">Pinouts - Component List and Chipset Pin-Outs for Analog Joypad, SCPH-1200</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-analog-joypad-scph-110">Pinouts - Component List and Chipset Pin-Outs for Analog Joypad, SCPH-110</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-namco-lightgun-npc-103">Pinouts - Component List and Chipset Pin-Outs for Namco Lightgun, NPC-103</a><br/>
|
||||
<a href="../pinouts/#pinouts-component-list-and-chipset-pin-outs-for-multitap-scph-1070">Pinouts - Component List and Chipset Pin-Outs for Multitap, SCPH-1070</a><br/>
|
||||
<a href="../pinouts/#pinouts-memory-cards">Pinouts - Memory Cards</a><br/>
|
||||
<a href="../pinouts/#mods-nocash-psx-xboo-upload">Mods - Nocash PSX-XBOO Upload</a><br/>
|
||||
<a href="../pinouts/#mods-palntsc-color-mods">Mods - PAL/NTSC Color Mods</a><br/>
|
||||
<a href="./">About & Credits</a><br/></p>
|
||||
<p>[extracted from no$psx v2.0 documentation]<br/>
|
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|
||||
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|
||||
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|
||||
PlayStation Specifications - psx-spx
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
Arcade Cabinets
|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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PlayStation Specifications - psx-spx
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|
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|
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|
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|
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|
||||
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|
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|
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Arcade Cabinets
|
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|
||||
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|
||||
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Arcade Cabinets
|
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|
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||||
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|
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|
||||
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||||
PSX-Based Arcade Boards
|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<a class="md-nav__link" href="#rom-vs-cdrom">
|
||||
ROM vs CDROM
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu">
|
||||
SPU
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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About & Credits
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|
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|
||||
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|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
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||||
</div>
|
||||
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|
||||
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|
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||||
Table of contents
|
||||
</label>
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||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psx-based-arcade-boards">
|
||||
PSX-Based Arcade Boards
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cpu">
|
||||
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|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#gpu">
|
||||
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|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#rom-vs-cdrom">
|
||||
ROM vs CDROM
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu">
|
||||
SPU
|
||||
</a>
|
||||
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|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#controls">
|
||||
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|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/arcadecabinets.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="arcade-cabinets">Arcade Cabinets</h1>
|
||||
<h4 id="psx-based-arcade-boards">PSX-Based Arcade Boards</h4>
|
||||
<pre><code> Namco System 11, System 12 (and System 10?)
|
||||
Capcom/Sony ZN-1, ZN-2
|
||||
Konami GV, Konami GQ
|
||||
Taito FX-1A, Taito FX-1B
|
||||
Atlus PSX, PS Arcade 95, Tecmo TPS
|
||||
</code></pre>
|
||||
<h4 id="cpu">CPU</h4>
|
||||
<p>Same as in PSX. Except, one board is said to be having the CPU clocked at
|
||||
48MHz, instead of 33MHz???<br/></p>
|
||||
<h4 id="gpu">GPU</h4>
|
||||
<p>Same as in PSX. Except, most or all boards are said to have 2MB VRAM instead of
|
||||
1MB. Unknown how the extra VRAM is accessed... maybe as Y=512..1023... (though
|
||||
the PSX VRAM transfer commands are limited to 9bit Ysiz values, but maybe Y
|
||||
coordinates can be 10bit wide).<br/></p>
|
||||
<h4 id="rom-vs-cdrom">ROM vs CDROM</h4>
|
||||
<p>Arcade games are stored on ROM (or FLASH) instead of using CDROM drives.<br/></p>
|
||||
<h4 id="spu">SPU</h4>
|
||||
<p>Most PSX-based arcade boards are having the PSX-SPU replaced by a different
|
||||
sound chip (with each arcade manufacturer using their own custom sound chip,
|
||||
often controlled by a separate sound CPU).<br/></p>
|
||||
<h4 id="controls">Controls</h4>
|
||||
<p>Arcade boards are typically having digital joysticks instead of joypads, with
|
||||
differently named buttons (instead of /\,[],(),>\<), probably accessed via
|
||||
custom I/O ports (instead of serial transmission)? Plus additional coin inputs
|
||||
and DIP switches.<br/></p>
|
||||
<p>Note: There's no documentation for those arcade boards yet, however, it might
|
||||
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<script id="__config" type="application/json">{"base": "..", "features": [], "translations": {"clipboard.copy": "Copy to clipboard", "clipboard.copied": "Copied to clipboard", "search.config.lang": "en", "search.config.pipeline": "trimmer, stopWordFilter", "search.config.separator": "[\\s\\-]+", "search.placeholder": "Search", "search.result.placeholder": "Type to start searching", "search.result.none": "No matching documents", "search.result.one": "1 matching document", "search.result.other": "# matching documents", "search.result.more.one": "1 more on this page", "search.result.more.other": "# more on this page", "search.result.term.missing": "Missing"}, "search": "../assets/javascripts/workers/search.fe42c31b.min.js", "version": null}</script>
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/*!
|
||||
* Lunr languages, `Danish` language
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* https://github.com/MihaiValentin/lunr-languages
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*
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* Copyright 2014, Mihai Valentin
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* http://www.mozilla.org/MPL/
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*/
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/*!
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* based on
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* Snowball JavaScript Library v0.3
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* http://code.google.com/p/urim/
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* http://snowball.tartarus.org/
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*
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* Copyright 2010, Oleg Mazko
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* http://www.mozilla.org/MPL/
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*/
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|
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|
|
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|
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module.exports=require("./lunr.ja");
|
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!function(e,t){"function"==typeof define&&define.amd?define(t):"object"==typeof exports?module.exports=t():t()(e.lunr)}(this,function(){return function(e){e.multiLanguage=function(){for(var t=Array.prototype.slice.call(arguments),i=t.join("-"),r="",n=[],s=[],p=0;p<t.length;++p)"en"==t[p]?(r+="\\w",n.unshift(e.stopWordFilter),n.push(e.stemmer),s.push(e.stemmer)):(r+=e[t[p]].wordCharacters,e[t[p]].stopWordFilter&&n.unshift(e[t[p]].stopWordFilter),e[t[p]].stemmer&&(n.push(e[t[p]].stemmer),s.push(e[t[p]].stemmer)));var o=e.trimmerSupport.generateTrimmer(r);return e.Pipeline.registerFunction(o,"lunr-multi-trimmer-"+i),n.unshift(o),function(){this.pipeline.reset(),this.pipeline.add.apply(this.pipeline,n),this.searchPipeline&&(this.searchPipeline.reset(),this.searchPipeline.add.apply(this.searchPipeline,s))}}}});
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/*!
|
||||
* Lunr languages, `Norwegian` language
|
||||
* https://github.com/MihaiValentin/lunr-languages
|
||||
*
|
||||
* Copyright 2014, Mihai Valentin
|
||||
* http://www.mozilla.org/MPL/
|
||||
*/
|
||||
/*!
|
||||
* based on
|
||||
* Snowball JavaScript Library v0.3
|
||||
* http://code.google.com/p/urim/
|
||||
* http://snowball.tartarus.org/
|
||||
*
|
||||
* Copyright 2010, Oleg Mazko
|
||||
* http://www.mozilla.org/MPL/
|
||||
*/
|
||||
|
||||
!function(e,r){"function"==typeof define&&define.amd?define(r):"object"==typeof exports?module.exports=r():r()(e.lunr)}(this,function(){return function(e){if(void 0===e)throw new Error("Lunr is not present. Please include / require Lunr before this script.");if(void 0===e.stemmerSupport)throw new Error("Lunr stemmer support is not present. Please include / require Lunr stemmer support before this script.");e.no=function(){this.pipeline.reset(),this.pipeline.add(e.no.trimmer,e.no.stopWordFilter,e.no.stemmer),this.searchPipeline&&(this.searchPipeline.reset(),this.searchPipeline.add(e.no.stemmer))},e.no.wordCharacters="A-Za-zªºÀ-ÖØ-öø-ʸˠ-ˤᴀ-ᴥᴬ-ᵜᵢ-ᵥᵫ-ᵷᵹ-ᶾḀ-ỿⁱⁿₐ-ₜKÅℲⅎⅠ-ↈⱠ-ⱿꜢ-ꞇꞋ-ꞭꞰ-ꞷꟷ-ꟿꬰ-ꭚꭜ-ꭤff-stＡ-Ｚａ-ｚ",e.no.trimmer=e.trimmerSupport.generateTrimmer(e.no.wordCharacters),e.Pipeline.registerFunction(e.no.trimmer,"trimmer-no"),e.no.stemmer=function(){var r=e.stemmerSupport.Among,n=e.stemmerSupport.SnowballProgram,i=new function(){function e(){var e,r=w.cursor+3;if(a=w.limit,0<=r||r<=w.limit){for(s=r;;){if(e=w.cursor,w.in_grouping(d,97,248)){w.cursor=e;break}if(e>=w.limit)return;w.cursor=e+1}for(;!w.out_grouping(d,97,248);){if(w.cursor>=w.limit)return;w.cursor++}a=w.cursor,a<s&&(a=s)}}function i(){var e,r,n;if(w.cursor>=a&&(r=w.limit_backward,w.limit_backward=a,w.ket=w.cursor,e=w.find_among_b(m,29),w.limit_backward=r,e))switch(w.bra=w.cursor,e){case 1:w.slice_del();break;case 2:n=w.limit-w.cursor,w.in_grouping_b(c,98,122)?w.slice_del():(w.cursor=w.limit-n,w.eq_s_b(1,"k")&&w.out_grouping_b(d,97,248)&&w.slice_del());break;case 3:w.slice_from("er")}}function t(){var e,r=w.limit-w.cursor;w.cursor>=a&&(e=w.limit_backward,w.limit_backward=a,w.ket=w.cursor,w.find_among_b(u,2)?(w.bra=w.cursor,w.limit_backward=e,w.cursor=w.limit-r,w.cursor>w.limit_backward&&(w.cursor--,w.bra=w.cursor,w.slice_del())):w.limit_backward=e)}function o(){var e,r;w.cursor>=a&&(r=w.limit_backward,w.limit_backward=a,w.ket=w.cursor,e=w.find_among_b(l,11),e?(w.bra=w.cursor,w.limit_backward=r,1==e&&w.slice_del()):w.limit_backward=r)}var s,a,m=[new r("a",-1,1),new r("e",-1,1),new r("ede",1,1),new r("ande",1,1),new r("ende",1,1),new r("ane",1,1),new r("ene",1,1),new r("hetene",6,1),new r("erte",1,3),new r("en",-1,1),new r("heten",9,1),new r("ar",-1,1),new r("er",-1,1),new r("heter",12,1),new r("s",-1,2),new r("as",14,1),new r("es",14,1),new r("edes",16,1),new r("endes",16,1),new r("enes",16,1),new r("hetenes",19,1),new r("ens",14,1),new r("hetens",21,1),new r("ers",14,1),new r("ets",14,1),new r("et",-1,1),new r("het",25,1),new r("ert",-1,3),new r("ast",-1,1)],u=[new r("dt",-1,-1),new r("vt",-1,-1)],l=[new r("leg",-1,1),new r("eleg",0,1),new r("ig",-1,1),new r("eig",2,1),new r("lig",2,1),new r("elig",4,1),new r("els",-1,1),new r("lov",-1,1),new r("elov",7,1),new r("slov",7,1),new r("hetslov",9,1)],d=[17,65,16,1,0,0,0,0,0,0,0,0,0,0,0,0,48,0,128],c=[119,125,149,1],w=new n;this.setCurrent=function(e){w.setCurrent(e)},this.getCurrent=function(){return w.getCurrent()},this.stem=function(){var r=w.cursor;return e(),w.limit_backward=r,w.cursor=w.limit,i(),w.cursor=w.limit,t(),w.cursor=w.limit,o(),!0}};return function(e){return"function"==typeof e.update?e.update(function(e){return i.setCurrent(e),i.stem(),i.getCurrent()}):(i.setCurrent(e),i.stem(),i.getCurrent())}}(),e.Pipeline.registerFunction(e.no.stemmer,"stemmer-no"),e.no.stopWordFilter=e.generateStopWordFilter("alle at av bare begge ble blei bli blir blitt både båe da de deg dei deim deira deires dem den denne der dere deres det dette di din disse ditt du dykk dykkar då eg ein eit eitt eller elles en enn er et ett etter for fordi fra før ha hadde han hans har hennar henne hennes her hjå ho hoe honom hoss hossen hun hva hvem hver hvilke hvilken hvis hvor hvordan hvorfor i ikke ikkje ikkje ingen ingi inkje inn inni ja jeg kan kom korleis korso kun kunne kva kvar kvarhelst kven kvi kvifor man mange me med medan meg meget mellom men mi min mine mitt mot mykje ned no noe noen noka noko nokon nokor nokre nå når og også om opp oss over på samme seg selv si si sia sidan siden sin sine sitt sjøl skal skulle slik so som som somme somt så sånn til um upp ut uten var vart varte ved vere verte vi vil ville vore vors vort vår være være vært å".split(" ")),e.Pipeline.registerFunction(e.no.stopWordFilter,"stopWordFilter-no")}});
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|
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!function(r,t){"function"==typeof define&&define.amd?define(t):"object"==typeof exports?module.exports=t():t()(r.lunr)}(this,function(){return function(r){r.stemmerSupport={Among:function(r,t,i,s){if(this.toCharArray=function(r){for(var t=r.length,i=new Array(t),s=0;s<t;s++)i[s]=r.charCodeAt(s);return i},!r&&""!=r||!t&&0!=t||!i)throw"Bad Among initialisation: s:"+r+", substring_i: "+t+", result: "+i;this.s_size=r.length,this.s=this.toCharArray(r),this.substring_i=t,this.result=i,this.method=s},SnowballProgram:function(){var r;return{bra:0,ket:0,limit:0,cursor:0,limit_backward:0,setCurrent:function(t){r=t,this.cursor=0,this.limit=t.length,this.limit_backward=0,this.bra=this.cursor,this.ket=this.limit},getCurrent:function(){var t=r;return r=null,t},in_grouping:function(t,i,s){if(this.cursor<this.limit){var e=r.charCodeAt(this.cursor);if(e<=s&&e>=i&&(e-=i,t[e>>3]&1<<(7&e)))return this.cursor++,!0}return!1},in_grouping_b:function(t,i,s){if(this.cursor>this.limit_backward){var e=r.charCodeAt(this.cursor-1);if(e<=s&&e>=i&&(e-=i,t[e>>3]&1<<(7&e)))return this.cursor--,!0}return!1},out_grouping:function(t,i,s){if(this.cursor<this.limit){var e=r.charCodeAt(this.cursor);if(e>s||e<i)return this.cursor++,!0;if(e-=i,!(t[e>>3]&1<<(7&e)))return this.cursor++,!0}return!1},out_grouping_b:function(t,i,s){if(this.cursor>this.limit_backward){var e=r.charCodeAt(this.cursor-1);if(e>s||e<i)return this.cursor--,!0;if(e-=i,!(t[e>>3]&1<<(7&e)))return this.cursor--,!0}return!1},eq_s:function(t,i){if(this.limit-this.cursor<t)return!1;for(var s=0;s<t;s++)if(r.charCodeAt(this.cursor+s)!=i.charCodeAt(s))return!1;return this.cursor+=t,!0},eq_s_b:function(t,i){if(this.cursor-this.limit_backward<t)return!1;for(var s=0;s<t;s++)if(r.charCodeAt(this.cursor-t+s)!=i.charCodeAt(s))return!1;return this.cursor-=t,!0},find_among:function(t,i){for(var s=0,e=i,n=this.cursor,u=this.limit,o=0,h=0,c=!1;;){for(var a=s+(e-s>>1),f=0,l=o<h?o:h,_=t[a],m=l;m<_.s_size;m++){if(n+l==u){f=-1;break}if(f=r.charCodeAt(n+l)-_.s[m])break;l++}if(f<0?(e=a,h=l):(s=a,o=l),e-s<=1){if(s>0||e==s||c)break;c=!0}}for(;;){var _=t[s];if(o>=_.s_size){if(this.cursor=n+_.s_size,!_.method)return _.result;var b=_.method();if(this.cursor=n+_.s_size,b)return _.result}if((s=_.substring_i)<0)return 0}},find_among_b:function(t,i){for(var s=0,e=i,n=this.cursor,u=this.limit_backward,o=0,h=0,c=!1;;){for(var a=s+(e-s>>1),f=0,l=o<h?o:h,_=t[a],m=_.s_size-1-l;m>=0;m--){if(n-l==u){f=-1;break}if(f=r.charCodeAt(n-1-l)-_.s[m])break;l++}if(f<0?(e=a,h=l):(s=a,o=l),e-s<=1){if(s>0||e==s||c)break;c=!0}}for(;;){var _=t[s];if(o>=_.s_size){if(this.cursor=n-_.s_size,!_.method)return _.result;var b=_.method();if(this.cursor=n-_.s_size,b)return _.result}if((s=_.substring_i)<0)return 0}},replace_s:function(t,i,s){var e=s.length-(i-t),n=r.substring(0,t),u=r.substring(i);return r=n+s+u,this.limit+=e,this.cursor>=i?this.cursor+=e:this.cursor>t&&(this.cursor=t),e},slice_check:function(){if(this.bra<0||this.bra>this.ket||this.ket>this.limit||this.limit>r.length)throw"faulty slice operation"},slice_from:function(r){this.slice_check(),this.replace_s(this.bra,this.ket,r)},slice_del:function(){this.slice_from("")},insert:function(r,t,i){var s=this.replace_s(r,t,i);r<=this.bra&&(this.bra+=s),r<=this.ket&&(this.ket+=s)},slice_to:function(){return this.slice_check(),r.substring(this.bra,this.ket)},eq_v_b:function(r){return this.eq_s_b(r.length,r)}}}},r.trimmerSupport={generateTrimmer:function(r){var t=new RegExp("^[^"+r+"]+"),i=new RegExp("[^"+r+"]+$");return function(r){return"function"==typeof r.update?r.update(function(r){return r.replace(t,"").replace(i,"")}):r.replace(t,"").replace(i,"")}}}}});
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*!
|
||||
* Lunr languages, `Swedish` language
|
||||
* https://github.com/MihaiValentin/lunr-languages
|
||||
*
|
||||
* Copyright 2014, Mihai Valentin
|
||||
* http://www.mozilla.org/MPL/
|
||||
*/
|
||||
/*!
|
||||
* based on
|
||||
* Snowball JavaScript Library v0.3
|
||||
* http://code.google.com/p/urim/
|
||||
* http://snowball.tartarus.org/
|
||||
*
|
||||
* Copyright 2010, Oleg Mazko
|
||||
* http://www.mozilla.org/MPL/
|
||||
*/
|
||||
|
||||
!function(e,r){"function"==typeof define&&define.amd?define(r):"object"==typeof exports?module.exports=r():r()(e.lunr)}(this,function(){return function(e){if(void 0===e)throw new Error("Lunr is not present. Please include / require Lunr before this script.");if(void 0===e.stemmerSupport)throw new Error("Lunr stemmer support is not present. Please include / require Lunr stemmer support before this script.");e.sv=function(){this.pipeline.reset(),this.pipeline.add(e.sv.trimmer,e.sv.stopWordFilter,e.sv.stemmer),this.searchPipeline&&(this.searchPipeline.reset(),this.searchPipeline.add(e.sv.stemmer))},e.sv.wordCharacters="A-Za-zªºÀ-ÖØ-öø-ʸˠ-ˤᴀ-ᴥᴬ-ᵜᵢ-ᵥᵫ-ᵷᵹ-ᶾḀ-ỿⁱⁿₐ-ₜKÅℲⅎⅠ-ↈⱠ-ⱿꜢ-ꞇꞋ-ꞭꞰ-ꞷꟷ-ꟿꬰ-ꭚꭜ-ꭤff-stＡ-Ｚａ-ｚ",e.sv.trimmer=e.trimmerSupport.generateTrimmer(e.sv.wordCharacters),e.Pipeline.registerFunction(e.sv.trimmer,"trimmer-sv"),e.sv.stemmer=function(){var r=e.stemmerSupport.Among,n=e.stemmerSupport.SnowballProgram,t=new function(){function e(){var e,r=w.cursor+3;if(o=w.limit,0<=r||r<=w.limit){for(a=r;;){if(e=w.cursor,w.in_grouping(l,97,246)){w.cursor=e;break}if(w.cursor=e,w.cursor>=w.limit)return;w.cursor++}for(;!w.out_grouping(l,97,246);){if(w.cursor>=w.limit)return;w.cursor++}o=w.cursor,o<a&&(o=a)}}function t(){var e,r=w.limit_backward;if(w.cursor>=o&&(w.limit_backward=o,w.cursor=w.limit,w.ket=w.cursor,e=w.find_among_b(u,37),w.limit_backward=r,e))switch(w.bra=w.cursor,e){case 1:w.slice_del();break;case 2:w.in_grouping_b(d,98,121)&&w.slice_del()}}function i(){var e=w.limit_backward;w.cursor>=o&&(w.limit_backward=o,w.cursor=w.limit,w.find_among_b(c,7)&&(w.cursor=w.limit,w.ket=w.cursor,w.cursor>w.limit_backward&&(w.bra=--w.cursor,w.slice_del())),w.limit_backward=e)}function s(){var e,r;if(w.cursor>=o){if(r=w.limit_backward,w.limit_backward=o,w.cursor=w.limit,w.ket=w.cursor,e=w.find_among_b(m,5))switch(w.bra=w.cursor,e){case 1:w.slice_del();break;case 2:w.slice_from("lös");break;case 3:w.slice_from("full")}w.limit_backward=r}}var a,o,u=[new r("a",-1,1),new r("arna",0,1),new r("erna",0,1),new r("heterna",2,1),new r("orna",0,1),new r("ad",-1,1),new r("e",-1,1),new r("ade",6,1),new r("ande",6,1),new r("arne",6,1),new r("are",6,1),new r("aste",6,1),new r("en",-1,1),new r("anden",12,1),new r("aren",12,1),new r("heten",12,1),new r("ern",-1,1),new r("ar",-1,1),new r("er",-1,1),new r("heter",18,1),new r("or",-1,1),new r("s",-1,2),new r("as",21,1),new r("arnas",22,1),new r("ernas",22,1),new r("ornas",22,1),new r("es",21,1),new r("ades",26,1),new r("andes",26,1),new r("ens",21,1),new r("arens",29,1),new r("hetens",29,1),new r("erns",21,1),new r("at",-1,1),new r("andet",-1,1),new r("het",-1,1),new r("ast",-1,1)],c=[new r("dd",-1,-1),new r("gd",-1,-1),new r("nn",-1,-1),new r("dt",-1,-1),new r("gt",-1,-1),new r("kt",-1,-1),new r("tt",-1,-1)],m=[new r("ig",-1,1),new r("lig",0,1),new r("els",-1,1),new r("fullt",-1,3),new r("löst",-1,2)],l=[17,65,16,1,0,0,0,0,0,0,0,0,0,0,0,0,24,0,32],d=[119,127,149],w=new n;this.setCurrent=function(e){w.setCurrent(e)},this.getCurrent=function(){return w.getCurrent()},this.stem=function(){var r=w.cursor;return e(),w.limit_backward=r,w.cursor=w.limit,t(),w.cursor=w.limit,i(),w.cursor=w.limit,s(),!0}};return function(e){return"function"==typeof e.update?e.update(function(e){return t.setCurrent(e),t.stem(),t.getCurrent()}):(t.setCurrent(e),t.stem(),t.getCurrent())}}(),e.Pipeline.registerFunction(e.sv.stemmer,"stemmer-sv"),e.sv.stopWordFilter=e.generateStopWordFilter("alla allt att av blev bli blir blivit de dem den denna deras dess dessa det detta dig din dina ditt du där då efter ej eller en er era ert ett från för ha hade han hans har henne hennes hon honom hur här i icke ingen inom inte jag ju kan kunde man med mellan men mig min mina mitt mot mycket ni nu när någon något några och om oss på samma sedan sig sin sina sitta själv skulle som så sådan sådana sådant till under upp ut utan vad var vara varför varit varje vars vart vem vi vid vilka vilkas vilken vilket vår våra vårt än är åt över".split(" ")),e.Pipeline.registerFunction(e.sv.stopWordFilter,"stopWordFilter-sv")}});
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1 @@
|
|||
!function(e,r){"function"==typeof define&&define.amd?define(r):"object"==typeof exports?module.exports=r():r()(e.lunr)}(this,function(){return function(e){if(void 0===e)throw new Error("Lunr is not present. Please include / require Lunr before this script.");if(void 0===e.stemmerSupport)throw new Error("Lunr stemmer support is not present. Please include / require Lunr stemmer support before this script.");e.vi=function(){this.pipeline.reset(),this.pipeline.add(e.vi.stopWordFilter,e.vi.trimmer)},e.vi.wordCharacters="[A-Za-ẓ̀͐́͑̉̃̓ÂâÊêÔôĂ-ăĐ-đƠ-ơƯ-ư]",e.vi.trimmer=e.trimmerSupport.generateTrimmer(e.vi.wordCharacters),e.Pipeline.registerFunction(e.vi.trimmer,"trimmer-vi"),e.vi.stopWordFilter=e.generateStopWordFilter("là cái nhưng mà".split(" "))}});
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/**
|
||||
* export the module via AMD, CommonJS or as a browser global
|
||||
* Export code from https://github.com/umdjs/umd/blob/master/returnExports.js
|
||||
*/
|
||||
;(function (root, factory) {
|
||||
if (typeof define === 'function' && define.amd) {
|
||||
// AMD. Register as an anonymous module.
|
||||
define(factory)
|
||||
} else if (typeof exports === 'object') {
|
||||
/**
|
||||
* Node. Does not work with strict CommonJS, but
|
||||
* only CommonJS-like environments that support module.exports,
|
||||
* like Node.
|
||||
*/
|
||||
module.exports = factory()
|
||||
} else {
|
||||
// Browser globals (root is window)
|
||||
factory()(root.lunr);
|
||||
}
|
||||
}(this, function () {
|
||||
/**
|
||||
* Just return a value to define the module export.
|
||||
* This example returns an object, but the module
|
||||
* can return a function as the exported value.
|
||||
*/
|
||||
|
||||
return function(lunr) {
|
||||
// TinySegmenter 0.1 -- Super compact Japanese tokenizer in Javascript
|
||||
// (c) 2008 Taku Kudo <taku@chasen.org>
|
||||
// TinySegmenter is freely distributable under the terms of a new BSD licence.
|
||||
// For details, see http://chasen.org/~taku/software/TinySegmenter/LICENCE.txt
|
||||
|
||||
function TinySegmenter() {
|
||||
var patterns = {
|
||||
"[一二三四五六七八九十百千万億兆]":"M",
|
||||
"[一-龠々〆ヵヶ]":"H",
|
||||
"[ぁ-ん]":"I",
|
||||
"[ァ-ヴーｱ-ﾝﾞｰ]":"K",
|
||||
"[a-zA-Zａ-ｚＡ-Ｚ]":"A",
|
||||
"[0-9０-９]":"N"
|
||||
}
|
||||
this.chartype_ = [];
|
||||
for (var i in patterns) {
|
||||
var regexp = new RegExp(i);
|
||||
this.chartype_.push([regexp, patterns[i]]);
|
||||
}
|
||||
|
||||
this.BIAS__ = -332
|
||||
this.BC1__ = {"HH":6,"II":2461,"KH":406,"OH":-1378};
|
||||
this.BC2__ = {"AA":-3267,"AI":2744,"AN":-878,"HH":-4070,"HM":-1711,"HN":4012,"HO":3761,"IA":1327,"IH":-1184,"II":-1332,"IK":1721,"IO":5492,"KI":3831,"KK":-8741,"MH":-3132,"MK":3334,"OO":-2920};
|
||||
this.BC3__ = {"HH":996,"HI":626,"HK":-721,"HN":-1307,"HO":-836,"IH":-301,"KK":2762,"MK":1079,"MM":4034,"OA":-1652,"OH":266};
|
||||
this.BP1__ = {"BB":295,"OB":304,"OO":-125,"UB":352};
|
||||
this.BP2__ = {"BO":60,"OO":-1762};
|
||||
this.BQ1__ = {"BHH":1150,"BHM":1521,"BII":-1158,"BIM":886,"BMH":1208,"BNH":449,"BOH":-91,"BOO":-2597,"OHI":451,"OIH":-296,"OKA":1851,"OKH":-1020,"OKK":904,"OOO":2965};
|
||||
this.BQ2__ = {"BHH":118,"BHI":-1159,"BHM":466,"BIH":-919,"BKK":-1720,"BKO":864,"OHH":-1139,"OHM":-181,"OIH":153,"UHI":-1146};
|
||||
this.BQ3__ = {"BHH":-792,"BHI":2664,"BII":-299,"BKI":419,"BMH":937,"BMM":8335,"BNN":998,"BOH":775,"OHH":2174,"OHM":439,"OII":280,"OKH":1798,"OKI":-793,"OKO":-2242,"OMH":-2402,"OOO":11699};
|
||||
this.BQ4__ = {"BHH":-3895,"BIH":3761,"BII":-4654,"BIK":1348,"BKK":-1806,"BMI":-3385,"BOO":-12396,"OAH":926,"OHH":266,"OHK":-2036,"ONN":-973};
|
||||
this.BW1__ = {",と":660,",同":727,"B1あ":1404,"B1同":542,"、と":660,"、同":727,"」と":1682,"あっ":1505,"いう":1743,"いっ":-2055,"いる":672,"うし":-4817,"うん":665,"から":3472,"がら":600,"こう":-790,"こと":2083,"こん":-1262,"さら":-4143,"さん":4573,"した":2641,"して":1104,"すで":-3399,"そこ":1977,"それ":-871,"たち":1122,"ため":601,"った":3463,"つい":-802,"てい":805,"てき":1249,"でき":1127,"です":3445,"では":844,"とい":-4915,"とみ":1922,"どこ":3887,"ない":5713,"なっ":3015,"など":7379,"なん":-1113,"にし":2468,"には":1498,"にも":1671,"に対":-912,"の一":-501,"の中":741,"ませ":2448,"まで":1711,"まま":2600,"まる":-2155,"やむ":-1947,"よっ":-2565,"れた":2369,"れで":-913,"をし":1860,"を見":731,"亡く":-1886,"京都":2558,"取り":-2784,"大き":-2604,"大阪":1497,"平方":-2314,"引き":-1336,"日本":-195,"本当":-2423,"毎日":-2113,"目指":-724,"Ｂ１あ":1404,"Ｂ１同":542,"｣と":1682};
|
||||
this.BW2__ = {"..":-11822,"11":-669,"――":-5730,"−−":-13175,"いう":-1609,"うか":2490,"かし":-1350,"かも":-602,"から":-7194,"かれ":4612,"がい":853,"がら":-3198,"きた":1941,"くな":-1597,"こと":-8392,"この":-4193,"させ":4533,"され":13168,"さん":-3977,"しい":-1819,"しか":-545,"した":5078,"して":972,"しな":939,"その":-3744,"たい":-1253,"たた":-662,"ただ":-3857,"たち":-786,"たと":1224,"たは":-939,"った":4589,"って":1647,"っと":-2094,"てい":6144,"てき":3640,"てく":2551,"ては":-3110,"ても":-3065,"でい":2666,"でき":-1528,"でし":-3828,"です":-4761,"でも":-4203,"とい":1890,"とこ":-1746,"とと":-2279,"との":720,"とみ":5168,"とも":-3941,"ない":-2488,"なが":-1313,"など":-6509,"なの":2614,"なん":3099,"にお":-1615,"にし":2748,"にな":2454,"によ":-7236,"に対":-14943,"に従":-4688,"に関":-11388,"のか":2093,"ので":-7059,"のに":-6041,"のの":-6125,"はい":1073,"はが":-1033,"はず":-2532,"ばれ":1813,"まし":-1316,"まで":-6621,"まれ":5409,"めて":-3153,"もい":2230,"もの":-10713,"らか":-944,"らし":-1611,"らに":-1897,"りし":651,"りま":1620,"れた":4270,"れて":849,"れば":4114,"ろう":6067,"われ":7901,"を通":-11877,"んだ":728,"んな":-4115,"一人":602,"一方":-1375,"一日":970,"一部":-1051,"上が":-4479,"会社":-1116,"出て":2163,"分の":-7758,"同党":970,"同日":-913,"大阪":-2471,"委員":-1250,"少な":-1050,"年度":-8669,"年間":-1626,"府県":-2363,"手権":-1982,"新聞":-4066,"日新":-722,"日本":-7068,"日米":3372,"曜日":-601,"朝鮮":-2355,"本人":-2697,"東京":-1543,"然と":-1384,"社会":-1276,"立て":-990,"第に":-1612,"米国":-4268,"１１":-669};
|
||||
this.BW3__ = {"あた":-2194,"あり":719,"ある":3846,"い.":-1185,"い。":-1185,"いい":5308,"いえ":2079,"いく":3029,"いた":2056,"いっ":1883,"いる":5600,"いわ":1527,"うち":1117,"うと":4798,"えと":1454,"か.":2857,"か。":2857,"かけ":-743,"かっ":-4098,"かに":-669,"から":6520,"かり":-2670,"が,":1816,"が、":1816,"がき":-4855,"がけ":-1127,"がっ":-913,"がら":-4977,"がり":-2064,"きた":1645,"けど":1374,"こと":7397,"この":1542,"ころ":-2757,"さい":-714,"さを":976,"し,":1557,"し、":1557,"しい":-3714,"した":3562,"して":1449,"しな":2608,"しま":1200,"す.":-1310,"す。":-1310,"する":6521,"ず,":3426,"ず、":3426,"ずに":841,"そう":428,"た.":8875,"た。":8875,"たい":-594,"たの":812,"たり":-1183,"たる":-853,"だ.":4098,"だ。":4098,"だっ":1004,"った":-4748,"って":300,"てい":6240,"てお":855,"ても":302,"です":1437,"でに":-1482,"では":2295,"とう":-1387,"とし":2266,"との":541,"とも":-3543,"どう":4664,"ない":1796,"なく":-903,"など":2135,"に,":-1021,"に、":-1021,"にし":1771,"にな":1906,"には":2644,"の,":-724,"の、":-724,"の子":-1000,"は,":1337,"は、":1337,"べき":2181,"まし":1113,"ます":6943,"まっ":-1549,"まで":6154,"まれ":-793,"らし":1479,"られ":6820,"るる":3818,"れ,":854,"れ、":854,"れた":1850,"れて":1375,"れば":-3246,"れる":1091,"われ":-605,"んだ":606,"んで":798,"カ月":990,"会議":860,"入り":1232,"大会":2217,"始め":1681,"市":965,"新聞":-5055,"日,":974,"日、":974,"社会":2024,"ｶ月":990};
|
||||
this.TC1__ = {"AAA":1093,"HHH":1029,"HHM":580,"HII":998,"HOH":-390,"HOM":-331,"IHI":1169,"IOH":-142,"IOI":-1015,"IOM":467,"MMH":187,"OOI":-1832};
|
||||
this.TC2__ = {"HHO":2088,"HII":-1023,"HMM":-1154,"IHI":-1965,"KKH":703,"OII":-2649};
|
||||
this.TC3__ = {"AAA":-294,"HHH":346,"HHI":-341,"HII":-1088,"HIK":731,"HOH":-1486,"IHH":128,"IHI":-3041,"IHO":-1935,"IIH":-825,"IIM":-1035,"IOI":-542,"KHH":-1216,"KKA":491,"KKH":-1217,"KOK":-1009,"MHH":-2694,"MHM":-457,"MHO":123,"MMH":-471,"NNH":-1689,"NNO":662,"OHO":-3393};
|
||||
this.TC4__ = {"HHH":-203,"HHI":1344,"HHK":365,"HHM":-122,"HHN":182,"HHO":669,"HIH":804,"HII":679,"HOH":446,"IHH":695,"IHO":-2324,"IIH":321,"III":1497,"IIO":656,"IOO":54,"KAK":4845,"KKA":3386,"KKK":3065,"MHH":-405,"MHI":201,"MMH":-241,"MMM":661,"MOM":841};
|
||||
this.TQ1__ = {"BHHH":-227,"BHHI":316,"BHIH":-132,"BIHH":60,"BIII":1595,"BNHH":-744,"BOHH":225,"BOOO":-908,"OAKK":482,"OHHH":281,"OHIH":249,"OIHI":200,"OIIH":-68};
|
||||
this.TQ2__ = {"BIHH":-1401,"BIII":-1033,"BKAK":-543,"BOOO":-5591};
|
||||
this.TQ3__ = {"BHHH":478,"BHHM":-1073,"BHIH":222,"BHII":-504,"BIIH":-116,"BIII":-105,"BMHI":-863,"BMHM":-464,"BOMH":620,"OHHH":346,"OHHI":1729,"OHII":997,"OHMH":481,"OIHH":623,"OIIH":1344,"OKAK":2792,"OKHH":587,"OKKA":679,"OOHH":110,"OOII":-685};
|
||||
this.TQ4__ = {"BHHH":-721,"BHHM":-3604,"BHII":-966,"BIIH":-607,"BIII":-2181,"OAAA":-2763,"OAKK":180,"OHHH":-294,"OHHI":2446,"OHHO":480,"OHIH":-1573,"OIHH":1935,"OIHI":-493,"OIIH":626,"OIII":-4007,"OKAK":-8156};
|
||||
this.TW1__ = {"につい":-4681,"東京都":2026};
|
||||
this.TW2__ = {"ある程":-2049,"いった":-1256,"ころが":-2434,"しょう":3873,"その後":-4430,"だって":-1049,"ていた":1833,"として":-4657,"ともに":-4517,"もので":1882,"一気に":-792,"初めて":-1512,"同時に":-8097,"大きな":-1255,"対して":-2721,"社会党":-3216};
|
||||
this.TW3__ = {"いただ":-1734,"してい":1314,"として":-4314,"につい":-5483,"にとっ":-5989,"に当た":-6247,"ので,":-727,"ので、":-727,"のもの":-600,"れから":-3752,"十二月":-2287};
|
||||
this.TW4__ = {"いう.":8576,"いう。":8576,"からな":-2348,"してい":2958,"たが,":1516,"たが、":1516,"ている":1538,"という":1349,"ました":5543,"ません":1097,"ようと":-4258,"よると":5865};
|
||||
this.UC1__ = {"A":484,"K":93,"M":645,"O":-505};
|
||||
this.UC2__ = {"A":819,"H":1059,"I":409,"M":3987,"N":5775,"O":646};
|
||||
this.UC3__ = {"A":-1370,"I":2311};
|
||||
this.UC4__ = {"A":-2643,"H":1809,"I":-1032,"K":-3450,"M":3565,"N":3876,"O":6646};
|
||||
this.UC5__ = {"H":313,"I":-1238,"K":-799,"M":539,"O":-831};
|
||||
this.UC6__ = {"H":-506,"I":-253,"K":87,"M":247,"O":-387};
|
||||
this.UP1__ = {"O":-214};
|
||||
this.UP2__ = {"B":69,"O":935};
|
||||
this.UP3__ = {"B":189};
|
||||
this.UQ1__ = {"BH":21,"BI":-12,"BK":-99,"BN":142,"BO":-56,"OH":-95,"OI":477,"OK":410,"OO":-2422};
|
||||
this.UQ2__ = {"BH":216,"BI":113,"OK":1759};
|
||||
this.UQ3__ = {"BA":-479,"BH":42,"BI":1913,"BK":-7198,"BM":3160,"BN":6427,"BO":14761,"OI":-827,"ON":-3212};
|
||||
this.UW1__ = {",":156,"、":156,"「":-463,"あ":-941,"う":-127,"が":-553,"き":121,"こ":505,"で":-201,"と":-547,"ど":-123,"に":-789,"の":-185,"は":-847,"も":-466,"や":-470,"よ":182,"ら":-292,"り":208,"れ":169,"を":-446,"ん":-137,"・":-135,"主":-402,"京":-268,"区":-912,"午":871,"国":-460,"大":561,"委":729,"市":-411,"日":-141,"理":361,"生":-408,"県":-386,"都":-718,"｢":-463,"･":-135};
|
||||
this.UW2__ = {",":-829,"、":-829,"〇":892,"「":-645,"」":3145,"あ":-538,"い":505,"う":134,"お":-502,"か":1454,"が":-856,"く":-412,"こ":1141,"さ":878,"ざ":540,"し":1529,"す":-675,"せ":300,"そ":-1011,"た":188,"だ":1837,"つ":-949,"て":-291,"で":-268,"と":-981,"ど":1273,"な":1063,"に":-1764,"の":130,"は":-409,"ひ":-1273,"べ":1261,"ま":600,"も":-1263,"や":-402,"よ":1639,"り":-579,"る":-694,"れ":571,"を":-2516,"ん":2095,"ア":-587,"カ":306,"キ":568,"ッ":831,"三":-758,"不":-2150,"世":-302,"中":-968,"主":-861,"事":492,"人":-123,"会":978,"保":362,"入":548,"初":-3025,"副":-1566,"北":-3414,"区":-422,"大":-1769,"天":-865,"太":-483,"子":-1519,"学":760,"実":1023,"小":-2009,"市":-813,"年":-1060,"強":1067,"手":-1519,"揺":-1033,"政":1522,"文":-1355,"新":-1682,"日":-1815,"明":-1462,"最":-630,"朝":-1843,"本":-1650,"東":-931,"果":-665,"次":-2378,"民":-180,"気":-1740,"理":752,"発":529,"目":-1584,"相":-242,"県":-1165,"立":-763,"第":810,"米":509,"自":-1353,"行":838,"西":-744,"見":-3874,"調":1010,"議":1198,"込":3041,"開":1758,"間":-1257,"｢":-645,"｣":3145,"ｯ":831,"ｱ":-587,"ｶ":306,"ｷ":568};
|
||||
this.UW3__ = {",":4889,"1":-800,"−":-1723,"、":4889,"々":-2311,"〇":5827,"」":2670,"〓":-3573,"あ":-2696,"い":1006,"う":2342,"え":1983,"お":-4864,"か":-1163,"が":3271,"く":1004,"け":388,"げ":401,"こ":-3552,"ご":-3116,"さ":-1058,"し":-395,"す":584,"せ":3685,"そ":-5228,"た":842,"ち":-521,"っ":-1444,"つ":-1081,"て":6167,"で":2318,"と":1691,"ど":-899,"な":-2788,"に":2745,"の":4056,"は":4555,"ひ":-2171,"ふ":-1798,"へ":1199,"ほ":-5516,"ま":-4384,"み":-120,"め":1205,"も":2323,"や":-788,"よ":-202,"ら":727,"り":649,"る":5905,"れ":2773,"わ":-1207,"を":6620,"ん":-518,"ア":551,"グ":1319,"ス":874,"ッ":-1350,"ト":521,"ム":1109,"ル":1591,"ロ":2201,"ン":278,"・":-3794,"一":-1619,"下":-1759,"世":-2087,"両":3815,"中":653,"主":-758,"予":-1193,"二":974,"人":2742,"今":792,"他":1889,"以":-1368,"低":811,"何":4265,"作":-361,"保":-2439,"元":4858,"党":3593,"全":1574,"公":-3030,"六":755,"共":-1880,"円":5807,"再":3095,"分":457,"初":2475,"別":1129,"前":2286,"副":4437,"力":365,"動":-949,"務":-1872,"化":1327,"北":-1038,"区":4646,"千":-2309,"午":-783,"協":-1006,"口":483,"右":1233,"各":3588,"合":-241,"同":3906,"和":-837,"員":4513,"国":642,"型":1389,"場":1219,"外":-241,"妻":2016,"学":-1356,"安":-423,"実":-1008,"家":1078,"小":-513,"少":-3102,"州":1155,"市":3197,"平":-1804,"年":2416,"広":-1030,"府":1605,"度":1452,"建":-2352,"当":-3885,"得":1905,"思":-1291,"性":1822,"戸":-488,"指":-3973,"政":-2013,"教":-1479,"数":3222,"文":-1489,"新":1764,"日":2099,"旧":5792,"昨":-661,"時":-1248,"曜":-951,"最":-937,"月":4125,"期":360,"李":3094,"村":364,"東":-805,"核":5156,"森":2438,"業":484,"氏":2613,"民":-1694,"決":-1073,"法":1868,"海":-495,"無":979,"物":461,"特":-3850,"生":-273,"用":914,"町":1215,"的":7313,"直":-1835,"省":792,"県":6293,"知":-1528,"私":4231,"税":401,"立":-960,"第":1201,"米":7767,"系":3066,"約":3663,"級":1384,"統":-4229,"総":1163,"線":1255,"者":6457,"能":725,"自":-2869,"英":785,"見":1044,"調":-562,"財":-733,"費":1777,"車":1835,"軍":1375,"込":-1504,"通":-1136,"選":-681,"郎":1026,"郡":4404,"部":1200,"金":2163,"長":421,"開":-1432,"間":1302,"関":-1282,"雨":2009,"電":-1045,"非":2066,"駅":1620,"１":-800,"｣":2670,"･":-3794,"ｯ":-1350,"ｱ":551,"ｸﾞ":1319,"ｽ":874,"ﾄ":521,"ﾑ":1109,"ﾙ":1591,"ﾛ":2201,"ﾝ":278};
|
||||
this.UW4__ = {",":3930,".":3508,"―":-4841,"、":3930,"。":3508,"〇":4999,"「":1895,"」":3798,"〓":-5156,"あ":4752,"い":-3435,"う":-640,"え":-2514,"お":2405,"か":530,"が":6006,"き":-4482,"ぎ":-3821,"く":-3788,"け":-4376,"げ":-4734,"こ":2255,"ご":1979,"さ":2864,"し":-843,"じ":-2506,"す":-731,"ず":1251,"せ":181,"そ":4091,"た":5034,"だ":5408,"ち":-3654,"っ":-5882,"つ":-1659,"て":3994,"で":7410,"と":4547,"な":5433,"に":6499,"ぬ":1853,"ね":1413,"の":7396,"は":8578,"ば":1940,"ひ":4249,"び":-4134,"ふ":1345,"へ":6665,"べ":-744,"ほ":1464,"ま":1051,"み":-2082,"む":-882,"め":-5046,"も":4169,"ゃ":-2666,"や":2795,"ょ":-1544,"よ":3351,"ら":-2922,"り":-9726,"る":-14896,"れ":-2613,"ろ":-4570,"わ":-1783,"を":13150,"ん":-2352,"カ":2145,"コ":1789,"セ":1287,"ッ":-724,"ト":-403,"メ":-1635,"ラ":-881,"リ":-541,"ル":-856,"ン":-3637,"・":-4371,"ー":-11870,"一":-2069,"中":2210,"予":782,"事":-190,"井":-1768,"人":1036,"以":544,"会":950,"体":-1286,"作":530,"側":4292,"先":601,"党":-2006,"共":-1212,"内":584,"円":788,"初":1347,"前":1623,"副":3879,"力":-302,"動":-740,"務":-2715,"化":776,"区":4517,"協":1013,"参":1555,"合":-1834,"和":-681,"員":-910,"器":-851,"回":1500,"国":-619,"園":-1200,"地":866,"場":-1410,"塁":-2094,"士":-1413,"多":1067,"大":571,"子":-4802,"学":-1397,"定":-1057,"寺":-809,"小":1910,"屋":-1328,"山":-1500,"島":-2056,"川":-2667,"市":2771,"年":374,"庁":-4556,"後":456,"性":553,"感":916,"所":-1566,"支":856,"改":787,"政":2182,"教":704,"文":522,"方":-856,"日":1798,"時":1829,"最":845,"月":-9066,"木":-485,"来":-442,"校":-360,"業":-1043,"氏":5388,"民":-2716,"気":-910,"沢":-939,"済":-543,"物":-735,"率":672,"球":-1267,"生":-1286,"産":-1101,"田":-2900,"町":1826,"的":2586,"目":922,"省":-3485,"県":2997,"空":-867,"立":-2112,"第":788,"米":2937,"系":786,"約":2171,"経":1146,"統":-1169,"総":940,"線":-994,"署":749,"者":2145,"能":-730,"般":-852,"行":-792,"規":792,"警":-1184,"議":-244,"谷":-1000,"賞":730,"車":-1481,"軍":1158,"輪":-1433,"込":-3370,"近":929,"道":-1291,"選":2596,"郎":-4866,"都":1192,"野":-1100,"銀":-2213,"長":357,"間":-2344,"院":-2297,"際":-2604,"電":-878,"領":-1659,"題":-792,"館":-1984,"首":1749,"高":2120,"｢":1895,"｣":3798,"･":-4371,"ｯ":-724,"ｰ":-11870,"ｶ":2145,"ｺ":1789,"ｾ":1287,"ﾄ":-403,"ﾒ":-1635,"ﾗ":-881,"ﾘ":-541,"ﾙ":-856,"ﾝ":-3637};
|
||||
this.UW5__ = {",":465,".":-299,"1":-514,"E2":-32768,"]":-2762,"、":465,"。":-299,"「":363,"あ":1655,"い":331,"う":-503,"え":1199,"お":527,"か":647,"が":-421,"き":1624,"ぎ":1971,"く":312,"げ":-983,"さ":-1537,"し":-1371,"す":-852,"だ":-1186,"ち":1093,"っ":52,"つ":921,"て":-18,"で":-850,"と":-127,"ど":1682,"な":-787,"に":-1224,"の":-635,"は":-578,"べ":1001,"み":502,"め":865,"ゃ":3350,"ょ":854,"り":-208,"る":429,"れ":504,"わ":419,"を":-1264,"ん":327,"イ":241,"ル":451,"ン":-343,"中":-871,"京":722,"会":-1153,"党":-654,"務":3519,"区":-901,"告":848,"員":2104,"大":-1296,"学":-548,"定":1785,"嵐":-1304,"市":-2991,"席":921,"年":1763,"思":872,"所":-814,"挙":1618,"新":-1682,"日":218,"月":-4353,"査":932,"格":1356,"機":-1508,"氏":-1347,"田":240,"町":-3912,"的":-3149,"相":1319,"省":-1052,"県":-4003,"研":-997,"社":-278,"空":-813,"統":1955,"者":-2233,"表":663,"語":-1073,"議":1219,"選":-1018,"郎":-368,"長":786,"間":1191,"題":2368,"館":-689,"１":-514,"Ｅ２":-32768,"｢":363,"ｲ":241,"ﾙ":451,"ﾝ":-343};
|
||||
this.UW6__ = {",":227,".":808,"1":-270,"E1":306,"、":227,"。":808,"あ":-307,"う":189,"か":241,"が":-73,"く":-121,"こ":-200,"じ":1782,"す":383,"た":-428,"っ":573,"て":-1014,"で":101,"と":-105,"な":-253,"に":-149,"の":-417,"は":-236,"も":-206,"り":187,"る":-135,"を":195,"ル":-673,"ン":-496,"一":-277,"中":201,"件":-800,"会":624,"前":302,"区":1792,"員":-1212,"委":798,"学":-960,"市":887,"広":-695,"後":535,"業":-697,"相":753,"社":-507,"福":974,"空":-822,"者":1811,"連":463,"郎":1082,"１":-270,"Ｅ１":306,"ﾙ":-673,"ﾝ":-496};
|
||||
|
||||
return this;
|
||||
}
|
||||
TinySegmenter.prototype.ctype_ = function(str) {
|
||||
for (var i in this.chartype_) {
|
||||
if (str.match(this.chartype_[i][0])) {
|
||||
return this.chartype_[i][1];
|
||||
}
|
||||
}
|
||||
return "O";
|
||||
}
|
||||
|
||||
TinySegmenter.prototype.ts_ = function(v) {
|
||||
if (v) { return v; }
|
||||
return 0;
|
||||
}
|
||||
|
||||
TinySegmenter.prototype.segment = function(input) {
|
||||
if (input == null || input == undefined || input == "") {
|
||||
return [];
|
||||
}
|
||||
var result = [];
|
||||
var seg = ["B3","B2","B1"];
|
||||
var ctype = ["O","O","O"];
|
||||
var o = input.split("");
|
||||
for (i = 0; i < o.length; ++i) {
|
||||
seg.push(o[i]);
|
||||
ctype.push(this.ctype_(o[i]))
|
||||
}
|
||||
seg.push("E1");
|
||||
seg.push("E2");
|
||||
seg.push("E3");
|
||||
ctype.push("O");
|
||||
ctype.push("O");
|
||||
ctype.push("O");
|
||||
var word = seg[3];
|
||||
var p1 = "U";
|
||||
var p2 = "U";
|
||||
var p3 = "U";
|
||||
for (var i = 4; i < seg.length - 3; ++i) {
|
||||
var score = this.BIAS__;
|
||||
var w1 = seg[i-3];
|
||||
var w2 = seg[i-2];
|
||||
var w3 = seg[i-1];
|
||||
var w4 = seg[i];
|
||||
var w5 = seg[i+1];
|
||||
var w6 = seg[i+2];
|
||||
var c1 = ctype[i-3];
|
||||
var c2 = ctype[i-2];
|
||||
var c3 = ctype[i-1];
|
||||
var c4 = ctype[i];
|
||||
var c5 = ctype[i+1];
|
||||
var c6 = ctype[i+2];
|
||||
score += this.ts_(this.UP1__[p1]);
|
||||
score += this.ts_(this.UP2__[p2]);
|
||||
score += this.ts_(this.UP3__[p3]);
|
||||
score += this.ts_(this.BP1__[p1 + p2]);
|
||||
score += this.ts_(this.BP2__[p2 + p3]);
|
||||
score += this.ts_(this.UW1__[w1]);
|
||||
score += this.ts_(this.UW2__[w2]);
|
||||
score += this.ts_(this.UW3__[w3]);
|
||||
score += this.ts_(this.UW4__[w4]);
|
||||
score += this.ts_(this.UW5__[w5]);
|
||||
score += this.ts_(this.UW6__[w6]);
|
||||
score += this.ts_(this.BW1__[w2 + w3]);
|
||||
score += this.ts_(this.BW2__[w3 + w4]);
|
||||
score += this.ts_(this.BW3__[w4 + w5]);
|
||||
score += this.ts_(this.TW1__[w1 + w2 + w3]);
|
||||
score += this.ts_(this.TW2__[w2 + w3 + w4]);
|
||||
score += this.ts_(this.TW3__[w3 + w4 + w5]);
|
||||
score += this.ts_(this.TW4__[w4 + w5 + w6]);
|
||||
score += this.ts_(this.UC1__[c1]);
|
||||
score += this.ts_(this.UC2__[c2]);
|
||||
score += this.ts_(this.UC3__[c3]);
|
||||
score += this.ts_(this.UC4__[c4]);
|
||||
score += this.ts_(this.UC5__[c5]);
|
||||
score += this.ts_(this.UC6__[c6]);
|
||||
score += this.ts_(this.BC1__[c2 + c3]);
|
||||
score += this.ts_(this.BC2__[c3 + c4]);
|
||||
score += this.ts_(this.BC3__[c4 + c5]);
|
||||
score += this.ts_(this.TC1__[c1 + c2 + c3]);
|
||||
score += this.ts_(this.TC2__[c2 + c3 + c4]);
|
||||
score += this.ts_(this.TC3__[c3 + c4 + c5]);
|
||||
score += this.ts_(this.TC4__[c4 + c5 + c6]);
|
||||
// score += this.ts_(this.TC5__[c4 + c5 + c6]);
|
||||
score += this.ts_(this.UQ1__[p1 + c1]);
|
||||
score += this.ts_(this.UQ2__[p2 + c2]);
|
||||
score += this.ts_(this.UQ3__[p3 + c3]);
|
||||
score += this.ts_(this.BQ1__[p2 + c2 + c3]);
|
||||
score += this.ts_(this.BQ2__[p2 + c3 + c4]);
|
||||
score += this.ts_(this.BQ3__[p3 + c2 + c3]);
|
||||
score += this.ts_(this.BQ4__[p3 + c3 + c4]);
|
||||
score += this.ts_(this.TQ1__[p2 + c1 + c2 + c3]);
|
||||
score += this.ts_(this.TQ2__[p2 + c2 + c3 + c4]);
|
||||
score += this.ts_(this.TQ3__[p3 + c1 + c2 + c3]);
|
||||
score += this.ts_(this.TQ4__[p3 + c2 + c3 + c4]);
|
||||
var p = "O";
|
||||
if (score > 0) {
|
||||
result.push(word);
|
||||
word = "";
|
||||
p = "B";
|
||||
}
|
||||
p1 = p2;
|
||||
p2 = p3;
|
||||
p3 = p;
|
||||
word += seg[i];
|
||||
}
|
||||
result.push(word);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
lunr.TinySegmenter = TinySegmenter;
|
||||
};
|
||||
|
||||
}));
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
After Width: | Height: | Size: 41 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
@media print {
|
||||
.md-typeset {
|
||||
font-size: 1rem !important;
|
||||
font-family: Verdana, Arial, Helvetica, sans-serif;
|
||||
}
|
||||
.md-typeset code {
|
||||
font-size: 1em !important;
|
||||
font-family: Menlo, Monaco, Consolas, "Courier New", monospace !important;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,643 @@
|
|||
|
||||
<!DOCTYPE html>
|
||||
|
||||
<html class="no-js" lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8"/>
|
||||
<meta content="width=device-width,initial-scale=1" name="viewport"/>
|
||||
<link href="https://psx-spx.consoledev.net/dmachannels/" rel="canonical"/>
|
||||
<link href="../assets/images/favicon.png" rel="icon"/>
|
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DMA Channels
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|
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|
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|
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|
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|
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|
||||
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|
||||
1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)
|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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</li>
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
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<div class="md-sidebar__scrollwrap">
|
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<div class="md-sidebar__inner">
|
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<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
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<label class="md-nav__title" for="__toc">
|
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<span class="md-nav__icon md-icon"></span>
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Table of contents
|
||||
</label>
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<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dma-register-summary">
|
||||
DMA Register Summary
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801080hn10h-d_madr-dma-base-address-channel-06-rw">
|
||||
1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801084hn10h-d_bcr-dma-block-control-channel-06-rw">
|
||||
1F801084h+N*10h - D#_BCR - DMA Block Control (Channel 0..6) (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801088hn10h-d_chcr-dma-channel-control-channel-06-rw">
|
||||
1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f8010f0h-dpcr-dma-control-register-rw">
|
||||
1F8010F0h - DPCR - DMA Control Register (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f8010f4h-dicr-dma-interrupt-register-rw">
|
||||
1F8010F4h - DICR - DMA Interrupt Register (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f8010f8h-usually-7ffac68bh-or-0bfac688h">
|
||||
1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f8010fch-usually-00fffff7h-maybe-otc-fill-value">
|
||||
1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#commonly-used-dma-control-register-values-for-starting-dma-transfers">
|
||||
Commonly used DMA Control Register values for starting DMA transfers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dma-transfer-rates">
|
||||
DMA Transfer Rates
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dram-hyper-page-mode">
|
||||
DRAM Hyper Page mode
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cpu-operation-during-dma">
|
||||
CPU Operation during DMA
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/dmachannels.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="dma-channels">DMA Channels</h1>
|
||||
<h4 id="dma-register-summary">DMA Register Summary</h4>
|
||||
<pre><code> 1F80108xh DMA0 channel 0 MDECin (RAM to MDEC)
|
||||
1F80109xh DMA1 channel 1 MDECout (MDEC to RAM)
|
||||
1F8010Axh DMA2 channel 2 GPU (lists + image data)
|
||||
1F8010Bxh DMA3 channel 3 CDROM (CDROM to RAM)
|
||||
1F8010Cxh DMA4 channel 4 SPU
|
||||
1F8010Dxh DMA5 channel 5 PIO (Expansion Port)
|
||||
1F8010Exh DMA6 channel 6 OTC (reverse clear OT) (GPU related)
|
||||
1F8010F0h DPCR - DMA Control register
|
||||
1F8010F4h DICR - DMA Interrupt register
|
||||
</code></pre>
|
||||
<p>These ports control DMA at the CPU-side. In most cases, you'll additionally
|
||||
need to initialize an address (and transfer direction, transfer enabled, etc.)
|
||||
at the remote-side (eg. at the GPU-side for DMA2).<br/></p>
|
||||
<h4 id="1f801080hn10h-d_madr-dma-base-address-channel-06-rw">1F801080h+N*10h - D#_MADR - DMA base address (Channel 0..6) (R/W)</h4>
|
||||
<pre><code> 0-23 Memory Address where the DMA will start reading from/writing to
|
||||
24-31 Not used (always zero)
|
||||
</code></pre>
|
||||
<p>In SyncMode=0, the hardware doesn't update the MADR registers (it will contain
|
||||
the start address even during and after the transfer) (unless Chopping is
|
||||
enabled, in that case it does update MADR, same does probably also happen when
|
||||
getting interrupted by a higher priority DMA channel).<br/>
|
||||
In SyncMode=1 and SyncMode=2, the hardware does update MADR (it will contain
|
||||
the start address of the currently transferred block; at transfer end, it'll
|
||||
hold the end-address in SyncMode=1, or the 00FFFFFFh end-code in SyncMode=2)<br/>
|
||||
Note: Address bit0-1 are writeable, but any updated current/end addresses are
|
||||
word-aligned with bit0-1 forced to zero.<br/></p>
|
||||
<h4 id="1f801084hn10h-d_bcr-dma-block-control-channel-06-rw">1F801084h+N*10h - D#_BCR - DMA Block Control (Channel 0..6) (R/W)</h4>
|
||||
<p>For SyncMode=0 (ie. for OTC and CDROM):<br/></p>
|
||||
<pre><code> 0-15 BC Number of words (0001h..FFFFh) (or 0=10000h words)
|
||||
16-31 0 Not used (usually 0 for OTC, or 1 ("one block") for CDROM)
|
||||
</code></pre>
|
||||
<p>For SyncMode=1 (ie. for MDEC, SPU, and GPU-vram-data):<br/></p>
|
||||
<pre><code> 0-15 BS Blocksize (words) ;for GPU/SPU max 10h, for MDEC max 20h
|
||||
16-31 BA Amount of blocks ;ie. total length = BS*BA words
|
||||
</code></pre>
|
||||
<p>For SyncMode=2 (ie. for GPU-command-lists):<br/></p>
|
||||
<pre><code> 0-31 0 Not used (should be zero) (transfer ends at END-CODE in list)
|
||||
</code></pre>
|
||||
<p>BC/BS/BA can be in range 0001h..FFFFh (or 0=10000h). For BS, take care not to
|
||||
set the blocksize larger than the buffer of the corresponding unit can hold.
|
||||
(GPU and SPU both have a 16-word buffer). A larger blocksize means faster
|
||||
transfer.<br/>
|
||||
SyncMode=1 decrements BA to zero, SyncMode=0 with chopping enabled decrements
|
||||
BC to zero (aside from that two cases, D#_BCR isn't changed during/after
|
||||
transfer).<br/></p>
|
||||
<h4 id="1f801088hn10h-d_chcr-dma-channel-control-channel-06-rw">1F801088h+N*10h - D#_CHCR - DMA Channel Control (Channel 0..6) (R/W)</h4>
|
||||
<pre><code> 0 Transfer Direction (0=To Main RAM, 1=From Main RAM)
|
||||
1 Memory Address Step (0=Forward;+4, 1=Backward;-4)
|
||||
2-7 Not used (always zero)
|
||||
8 Chopping Enable (0=Normal, 1=Chopping; run CPU during DMA gaps)
|
||||
9-10 SyncMode, Transfer Synchronisation/Mode (0-3):
|
||||
0 Start immediately and transfer all at once (used for CDROM, OTC)
|
||||
1 Sync blocks to DMA requests (used for MDEC, SPU, and GPU-data)
|
||||
2 Linked-List mode (used for GPU-command-lists)
|
||||
3 Reserved (not used)
|
||||
11-15 Not used (always zero)
|
||||
16-18 Chopping DMA Window Size (1 SHL N words)
|
||||
19 Not used (always zero)
|
||||
20-22 Chopping CPU Window Size (1 SHL N clks)
|
||||
23 Not used (always zero)
|
||||
24 Start/Busy (0=Stopped/Completed, 1=Start/Enable/Busy)
|
||||
25-27 Not used (always zero)
|
||||
28 Start/Trigger (0=Normal, 1=Manual Start; use for SyncMode=0)
|
||||
29 Unknown (R/W) Pause? (0=No, 1=Pause?) (For SyncMode=0 only?)
|
||||
30 Unknown (R/W)
|
||||
31 Not used (always zero)
|
||||
</code></pre>
|
||||
<p>The Start/Trigger bit is automatically cleared upon BEGIN of the transfer, this
|
||||
bit needs to be set only in SyncMode=0 (setting it in other SyncModes would
|
||||
force the first block to be transferred instantly without DRQ, which isn't
|
||||
desired).<br/>
|
||||
The Start/Busy bit is automatically cleared upon COMPLETION of the transfer,
|
||||
this bit must be always set for all SyncModes when starting a transfer.<br/>
|
||||
For DMA6/OTC there are some restrictions, D6_CHCR has only three
|
||||
read/write-able bits: Bit24,28,30. All other bits are read-only: Bit1 is always
|
||||
1 (step=backward), and the other bits are always 0.<br/></p>
|
||||
<h4 id="1f8010f0h-dpcr-dma-control-register-rw">1F8010F0h - DPCR - DMA Control Register (R/W)</h4>
|
||||
<pre><code> 0-2 DMA0, MDECin Priority (0..7; 0=Highest, 7=Lowest)
|
||||
3 DMA0, MDECin Master Enable (0=Disable, 1=Enable)
|
||||
4-6 DMA1, MDECout Priority (0..7; 0=Highest, 7=Lowest)
|
||||
7 DMA1, MDECout Master Enable (0=Disable, 1=Enable)
|
||||
8-10 DMA2, GPU Priority (0..7; 0=Highest, 7=Lowest)
|
||||
11 DMA2, GPU Master Enable (0=Disable, 1=Enable)
|
||||
12-14 DMA3, CDROM Priority (0..7; 0=Highest, 7=Lowest)
|
||||
15 DMA3, CDROM Master Enable (0=Disable, 1=Enable)
|
||||
16-18 DMA4, SPU Priority (0..7; 0=Highest, 7=Lowest)
|
||||
19 DMA4, SPU Master Enable (0=Disable, 1=Enable)
|
||||
20-22 DMA5, PIO Priority (0..7; 0=Highest, 7=Lowest)
|
||||
23 DMA5, PIO Master Enable (0=Disable, 1=Enable)
|
||||
24-26 DMA6, OTC Priority (0..7; 0=Highest, 7=Lowest)
|
||||
27 DMA6, OTC Master Enable (0=Disable, 1=Enable)
|
||||
28-30 Unknown, Priority Offset or so? (R/W)
|
||||
31 Unknown, no effect? (R/W)
|
||||
</code></pre>
|
||||
<p>Initial value on reset is 07654321h. If two or more channels have the same
|
||||
priority setting, then the priority is determined by the channel number
|
||||
(DMA0=Lowest, DMA6=Highest).<br/></p>
|
||||
<h4 id="1f8010f4h-dicr-dma-interrupt-register-rw">1F8010F4h - DICR - DMA Interrupt Register (R/W)</h4>
|
||||
<pre><code> 0-5 Unknown (read/write-able)
|
||||
6-14 Not used (always zero)
|
||||
15 Force IRQ (sets bit31) (0=None, 1=Force Bit31=1)
|
||||
16-22 IRQ Enable for DMA0..DMA6 (0=None, 1=Enable)
|
||||
23 IRQ Master Enable for DMA0..DMA6 (0=None, 1=Enable)
|
||||
24-30 IRQ Flags for DMA0..DMA6 (0=None, 1=IRQ) (Write 1 to reset)
|
||||
31 IRQ Master Flag (0=None, 1=IRQ) (Read only)
|
||||
</code></pre>
|
||||
<p>IRQ flags in Bit(24+n) are set upon DMAn completion - but caution - they are
|
||||
set ONLY if enabled in Bit(16+n).<br/>
|
||||
Bit31 is a simple readonly flag that follows the following rules:<br/></p>
|
||||
<pre><code> IF b15=1 OR (b23=1 AND (b16-22 AND b24-30)>0) THEN b31=1 ELSE b31=0
|
||||
</code></pre>
|
||||
<p>Upon 0-to-1 transition of Bit31, the IRQ3 flag (in Port 1F801070h) gets set.<br/>
|
||||
Bit24-30 are acknowledged (reset to zero) when writing a "1" to that bits (and,
|
||||
additionally, IRQ3 must be acknowledged via Port 1F801070h).<br/></p>
|
||||
<h4 id="1f8010f8h-usually-7ffac68bh-or-0bfac688h">1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)</h4>
|
||||
<pre><code> (changes to 7FE358D1h after DMA transfer)
|
||||
</code></pre>
|
||||
<h4 id="1f8010fch-usually-00fffff7h-maybe-otc-fill-value">1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)</h4>
|
||||
<pre><code> (stays so even after DMA transfer)
|
||||
</code></pre>
|
||||
<p>Contains strange read-only values (but not the usual "Garbage").<br/>
|
||||
Not yet tested during transfer, might be remaining length and address?<br/></p>
|
||||
<h4 id="commonly-used-dma-control-register-values-for-starting-dma-transfers">Commonly used DMA Control Register values for starting DMA transfers</h4>
|
||||
<pre><code> DMA0 MDEC.IN 01000201h (always)
|
||||
DMA1 MDEC.OUT 01000200h (always)
|
||||
DMA2 GPU 01000200h (VramRead), 01000201h (VramWrite), 01000401h (List)
|
||||
DMA3 CDROM 11000000h (normal), 11400100h (chopped, rarely used)
|
||||
DMA4 SPU 01000201h (write), 01000200h (read, rarely used)
|
||||
DMA5 PIO N/A (not used by any known games)
|
||||
DMA6 OTC 11000002h (always)
|
||||
</code></pre>
|
||||
<p>XXX: DMA2 values 01000201h (VramWrite), 01000401h (List) aren't 100% confirmed
|
||||
to be used by ALL existing games. All other values are always used as listed
|
||||
above.<br/></p>
|
||||
<h4 id="dma-transfer-rates">DMA Transfer Rates</h4>
|
||||
<pre><code> DMA0 MDEC.IN 1 clk/word ;0110h clks per 100h words ;\plus whatever
|
||||
DMA1 MDEC.OUT 1 clk/word ;0110h clks per 100h words ;/decompression time
|
||||
DMA2 GPU 1 clk/word ;0110h clks per 100h words ;-plus ...
|
||||
DMA3 CDROM/BIOS 24 clks/word ;1800h clks per 100h words ;\plus single/double
|
||||
DMA3 CDROM/GAMES 40 clks/word ;2800h clks per 100h words ;/speed sector rate
|
||||
DMA4 SPU 4 clks/word ;0420h clks per 100h words ;-plus ...
|
||||
DMA5 PIO 20 clks/word ;1400h clks per 100h words ;-not actually used
|
||||
DMA6 OTC 1 clk/word ;0110h clks per 100h words ;-plus nothing
|
||||
</code></pre>
|
||||
<p>MDEC decompression time is still unknown (may vary on RLE and color/mono).<br/>
|
||||
GPU polygon rendering time is unknown (may be quite slow for large polys).<br/>
|
||||
GPU vram read/write time is unknown (may vary on horizontal screen resolution).<br/>
|
||||
CDROM BIOS default is 24 clks, for some reason most games change it to 40 clks.<br/>
|
||||
SPU transfer is unknown (may have some extra delays).<br/>
|
||||
XXX is SPU really only 4 clks (theoretically SPU access should be slower)?<br/>
|
||||
PIO isn't used by any games (and if used: could be configured to other rates)<br/>
|
||||
OTC is just writing to RAM without extra overload.<br/>
|
||||
CDROM/SPU/PIO timings can be configured via Memory Control registers.<br/></p>
|
||||
<h4 id="dram-hyper-page-mode">DRAM Hyper Page mode</h4>
|
||||
<p>DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock
|
||||
cycle per word (effectively around 17 clks per 16 words, due to required row
|
||||
address loading, probably plus some further minimal overload due to refresh
|
||||
cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM
|
||||
access takes 1 opcode cycle plus 6 waitstates, ie. 7 cycles in total)<br/></p>
|
||||
<h4 id="cpu-operation-during-dma">CPU Operation during DMA</h4>
|
||||
<p>Basically, the CPU is stopped during DMA (theoretically, the CPU could be kept
|
||||
running when accessing only cache, scratchpad and on-chip I/O ports like DMA
|
||||
registers, and during the CDROM/SPU/PIO waitstates it could even access Main
|
||||
RAM, but these situations aren't supported).<br/>
|
||||
However, the CPU operation resumes during periods when DMA gets interrupted
|
||||
(ie. after SyncMode 1 blocks, after SyncMode 2 list entries) (or in SyncMode 0
|
||||
with Chopping enabled).<br/></p>
|
||||
</article>
|
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|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sonys-own-hardware-for-psx-can-be-also-used-with-psone">
|
||||
Sony's own hardware (for PSX) (can be also used with PSone)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sonys-own-hardware-for-psone">
|
||||
Sony's own hardware (for PSone)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sonys-own-devkits">
|
||||
Sony's own devkits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sn-system-psy-q-devkit-add-ons-scsi-cards">
|
||||
SN System / Psy-Q devkit add-ons / SCSI cards
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-licensed-hardware-japan">
|
||||
Sony Licensed Hardware (Japan)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-licensed-hardware-europe">
|
||||
Sony Licensed Hardware (Europe)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-licensed-hardware-usa">
|
||||
Sony Licensed Hardware (USA)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-licensed-hardware-asia">
|
||||
Sony Licensed Hardware (Asia)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#newer-hardware-add-ons">
|
||||
Newer hardware add-ons?
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#note">
|
||||
Note
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#software-cdrom-game-codes">
|
||||
Software (CDROM Game Codes)
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/hardwarenumbers.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="hardware-numbers">Hardware Numbers</h1>
|
||||
<h4 id="sonys-own-hardware-for-psx-can-be-also-used-with-psone">Sony's own hardware (for PSX) (can be also used with PSone)</h4>
|
||||
<pre><code> SCPH-1000 PlayStation (1994) (NTSC-J) (with S-Video)
|
||||
SCPH-1001 PlayStation (1995) (NTSC-U/C) (without S-Video)
|
||||
SCPH-1002 PlayStation (199x) (PAL) (without S-Video)
|
||||
SCPH-1010 Digital joypad (with short cable) (1994)
|
||||
SCPH-1020 Memory Card 1Mbits (1994)
|
||||
SCPH-1030 2-button Mouse (with short cable) (1994)
|
||||
SCPH-1040 Serial Link Cable
|
||||
SCPH-1050 RGB Cable (21-pin RGB Connector)
|
||||
SCPH-1060 RFU Cable/Adaptor (antennae connector) (NTSC-JP?) (1995)
|
||||
SCPH-1061 RFU Cable/Adaptor (antennae connector) (NTSC-US?)
|
||||
SCPH-1062 RFU Cable/Adaptor (antennae connector) (PAL)
|
||||
SCPH-1070 Multitap adaptor (four controllers/memory cards on one slot) (1995)
|
||||
SCPH-1080 Digital joypad (with longer cable) (1996)
|
||||
SCPH-1090 2-button Mouse (with longer cable) (1998)
|
||||
SCPH-1100 S Video Cable (1995)
|
||||
SCPH-1110 Analog Joystick (1996)
|
||||
SCPH-1120 RFU Adaptor (antennae connector) (NTSC-JP?) (1996)
|
||||
SCPH-1121 RFU Adaptor (antennae connector) (NTSC-US?)
|
||||
SCPH-1122 RFU Adaptor (antennae connector) (PAL)
|
||||
SCPH-1130 AC Power Cord (1996)
|
||||
SCPH-1140 AV Cable (1997)
|
||||
SCPH-1150 Analog Joypad (with one vibration motor, with red/green led) (1997)
|
||||
SCPH-1160 AV Adaptor (1997)
|
||||
SCPH-1170 Memory Card Triple Pack (three Memory Cards) (1996)
|
||||
SCPH-1180 Analog Joypad (without vibration motors, with red/green led)
|
||||
SCPH-119X Memory Card (X=different colors) (1997)
|
||||
SCPH-1200 Analog Joypad (with two vibration motors) (dualshock) (1997)
|
||||
SCPH-1210 Memory Card Case (1998)
|
||||
SCPH-2000 Keyboard/Mouse adapter (PS/2 to PSX controller port; for Lightspan)
|
||||
SCPH-3000 PlayStation (1995) (NTSC-J) (with the S-video output removed)
|
||||
SCPH-3500 PlayStation Fighting Box (console bundled with 2 controllers)(1996)
|
||||
SCPH-4000 PocketStation (Memory Card with LCD-screen) (1999)
|
||||
SCPH-4010 VPick (guitar-pick controller) (for Quest for Fame, Stolen Song)
|
||||
SCPH-4020 Long Strap for PocketStation (1999)
|
||||
SCPH-4030 Wrist Strap for PocketStation (1999)
|
||||
SCPH-5000 PlayStation (cost reduced) (Japan) (1996) ;\exists in these three
|
||||
SCPH-5001 PlayStation (cost reduced) (North America) ; regions only (not
|
||||
SCPH-5003 PlayStation (Asia) ;/in Europe)
|
||||
SCPH-5500 PlayStation without Cinch sockets (ie. AV Multi Out only) (1996)(J)
|
||||
SCPH-5501 "" North American version of the 5500
|
||||
SCPH-5502 "" European version of the 5500 (shipped with 1 digital joypad)
|
||||
SCPH-5552 Same as SCPH-5502 (but shipped with memcard and 2 digital joypads)
|
||||
SCPH-5903 PlayStation with built-in MPEG Video-CD decoder (Asia-only)
|
||||
SCPH-7000 PlayStation with Dualshock (1997) (Japan)
|
||||
SCPH-7001 PlayStation with Dualshock (199x) (North America)
|
||||
SCPH-7002 PlayStation with Dualshock (199x) (Europe)
|
||||
SCPH-7003 PlayStation with Dualshock (199x) (Asia)
|
||||
SCPH-7000W PlayStation (10 million model, not for sale, blue, region free)
|
||||
SCPH-7500 PlayStation with Dualshock, cost reduced (1999) (Japan)
|
||||
SCPH-7501 PlayStation with Dualshock, cost reduced (199x) (North America)
|
||||
SCPH-7502 PlayStation with Dualshock, cost reduced (199x) (Europe)
|
||||
SCPH-7503 PlayStation with Dualshock, cost reduced (199x) (Asia)
|
||||
SCPH-9000 PlayStation without Parallel I/O port (1999) (Japan)
|
||||
SCPH-9001 PlayStation without Parallel I/O port (199x) (North America)
|
||||
SCPH-9002 PlayStation without Parallel I/O port (199x) (Europe)
|
||||
SCPH-9003 PlayStation without Parallel I/O port (199x) (Asia)
|
||||
SCPH-9903 Rare SCEx-free PSX (Property of Sony Computer Entertainment, U/C)
|
||||
SFX-100 PlayStation Super Disc Prototype (with SNES chipset, no PSX chips)
|
||||
</code></pre>
|
||||
<h4 id="sonys-own-hardware-for-psone">Sony's own hardware (for PSone)</h4>
|
||||
<pre><code> SCPH-100 PSone (miniaturized PlayStation) (2000) (Japan)
|
||||
SCPH-101 PSone (miniaturized PlayStation) (200x) (North America)
|
||||
SCPH-102 PSone (miniaturized PlayStation) (200x) (Europe)
|
||||
SCPH-103 PSone (miniaturized PlayStation) (200x) (Asia)
|
||||
SCPH-102A PSone Europe (UK/AU, with A/V cable) ;\revision of "SCPH-102"
|
||||
SCPH-102B PSone Europe (UK, with RFU adaptor) ; with PM-41(2) board ?
|
||||
SCPH-102C PSone Europe (Continent, with A/V cable) ;/
|
||||
SCPH-110 Dual Analog Pad (for PSone) (Dualshock) (2000)
|
||||
SCPH-111 Multitap for PSone (seems to be quite rare, except in brazil)
|
||||
SCPH-112 AC adapter for PSone (In: 110-220VAC, Out: 7.5VDC, 2.0A, Japan)
|
||||
SCPH-113 AC adapter for PSone (In: 120VAC/60Hz, Out: 7.5VDC, 2.0A, USA)
|
||||
SCPH-114 AC adapter for PSone (In: 220-240VAC, Out: 7.5VDC, 2.0A, Europe)
|
||||
SCPH-115 AC adapter for PSone (In: 220-240VAC, Out: 7.5VDC, 2.0A, UK)
|
||||
SCPH-116 AC adapter for PSone (In: 220-240VAC, Out: 7.5VDC, 2.0A, Australia)
|
||||
SCPH-117 AC adapter for PSone (In: 110VAC, Out: 7.5VDC, 2.0A, Asia?)
|
||||
SCPH-120 AC adapter for PSone with LCD Screen (In: 100VAC, Out: 7.5VDC, 3.0A)
|
||||
SCPH-130 LCD Screen for PSone (to be attached to the console) (2001)
|
||||
SCPH-140 PSone and LCD screen combo (2001)
|
||||
SCPH-152 LCD screen for PSone (PAL SCPH-152C)
|
||||
SCPH-162 PSone and LCD screen (PAL SCPH-162C)
|
||||
SCPH-170 Car Adapter for PSone from car cigarette lighter (2001)
|
||||
SCPH-180 AV Connection Cable for LCD-screen's AV IN
|
||||
SCPH-10180K DoCoMo I-Mode Adaptor Cable (for internet via mobile phones)
|
||||
</code></pre>
|
||||
<h4 id="sonys-own-devkits">Sony's own devkits</h4>
|
||||
<pre><code> DTL-H201A Graphic Artist Board (ISA bus) (with NTSC video out)
|
||||
DTL-H240 PS-X RGB Cable
|
||||
DTL-H500C Digital joypad prototype (SNES-style design, with DB9 connector)
|
||||
DTL-H505 PS-X (Code Name) Target Box ? (PSX prototype, SCSI instead CDROM?)
|
||||
DTL-H700 Sound Artist Board (NuBus for Mac)
|
||||
DTL-H800 Sound Artist Board (PCI Bus for IBM) (with optical fibre sound out)
|
||||
DTL-H1000 Debugging Station (CD-R compatible PSX console) (Japan)
|
||||
DTL-H1001 Debugging Station (CD-R compatible PSX console) (North America)
|
||||
DTL-H1002 Debugging Station (CD-R compatible PSX console) (Europe)
|
||||
DTL-H1030 Mouse ?
|
||||
DTL-H1040 Link Cable ?
|
||||
DTL-H1050 RGB Cable ?
|
||||
DTL-H110x Debugging Station revision? (DC-powered)
|
||||
DTL-H120x Debugging Station revision? (AC-powered)
|
||||
DTL-H1500 Stand-Alone Box ? With ethernet, for SGI Workstation ?
|
||||
DTL-H2000 Dev board v1 (PSX on two ISA carts) (old pre-retail)
|
||||
DTL-H2010 Black External CDROM Drive for DTL-H2000 (CD-R compatible)
|
||||
DTL-H2040 Memory Box ?
|
||||
DTL-H2050 Adaptor for Controller port ?
|
||||
DTL-H2060 Serial Link cable
|
||||
DTL-H2070 RGB Cable ?
|
||||
DTL-H2080 Controller Box (joypad/memcard adaptor for DTL-H2000/DTL-xxxx?)
|
||||
DTL-H2500 Dev board (PCI bus)
|
||||
DTL-H2510 Gray Internal CDROM Drive for DTL-H2500/DTL-H2700 (CD-R compatible)
|
||||
DTL-H2700 Dev board (ISA bus) (CPU, ANALYZER ...?)
|
||||
DTL-H3000 Net Yaroze (hobby programmer dev kit) (Japan)
|
||||
DTL-H3001 Net Yaroze (hobby programmer dev kit) (North America)
|
||||
DTL-H3002 Net Yaroze (hobby programmer dev kit) (Europe)
|
||||
DTL-H3020 Access Card (for yaroze)
|
||||
DTL-H3050 Communication Cable (link port to rs232, for yaroze)
|
||||
DTL-D2020 Documentation: BUILD CD (Manual of Programmer's Tool)
|
||||
DTL-D2120 Documentation: (Manual of Programmer's Tool)
|
||||
DTL-D2130 Documentation: PsyQ (Manual of Programmer's Tool)
|
||||
DTL-D2130 Documentation: SdevTC (Manual of Programmer's Tool)
|
||||
DTL-D2140A Documentation: Ver.1.0 (Manual of Programmer's Tool)
|
||||
DTL-D2150A Documentation: Ver.2.0 (Manual of Programmer's Tool)
|
||||
</code></pre>
|
||||
<h4 id="sn-system-psy-q-devkit-add-ons-scsi-cards">SN System / Psy-Q devkit add-ons / SCSI cards</h4>
|
||||
<pre><code> DTL-S510B Unknown (another CDROM emulator version?)
|
||||
DTL-S2020 CD-ROM EMULATOR for DTL-H2000/DTL-H2500/DTL-H2700
|
||||
</code></pre>
|
||||
<h4 id="sony-licensed-hardware-japan">Sony Licensed Hardware (Japan)</h4>
|
||||
<pre><code> SLPH-00001 Namco neGcon (white) (NPC-101), Twist controller (SLEH-0003)
|
||||
SLPH-00002 Hori Fighting stick, digital stick with autofire/slowmotion/rumble
|
||||
SLPH-00003 ASCII Fighter stick V, psx-shaped digital stick (SLEH-0002)
|
||||
SLPH-00004 Sunsoft Sunstation pad, digital pad with autofire/slowmotion
|
||||
SLPH-00005 ASCII ASCIIPAD V, digital pad with autofire/slowmotion
|
||||
SLPH-00006 Imagineer Sandapaddo ThunderPad
|
||||
SLPH-00007 SANKYO N.ASUKA aka Nasca Pachinco Handle, bizarre paddle
|
||||
SLPH-00008 Spital SANGYO Programmable joystick
|
||||
SLPH-00009 Hori Fighting commander 2way controller
|
||||
SLPH-00010 Optec Super Pro Commander
|
||||
SLPH-00011 Super Pro Commander Accessory / Extended memo repack memory
|
||||
SLPH-00012 Hori Fighting Commander 10B Pad (gray), digital pad with extras
|
||||
SLPH-00013 Konami Hyper Blaster (green) ;\IRQ10-based Lightgun
|
||||
SLPH-00014 Konami Hyper Blaster (black) ;/(SLEH-0005/SLUH-00017)
|
||||
SLPH-00015 Namco Volume controller, paddle with 2 buttons
|
||||
SLPH-00016 Waka Up Scan Converter "[chiyo] clean! peripheral equipment?"
|
||||
SLPH-00017 Hori Fighting Commander 10B Pad (black), digital pad with extras
|
||||
SLPH-00018 Hori Real Arcade Stick, digital stick, small L1/L2 (HPS-10)
|
||||
SLPH-00019 Konami Hyperstick
|
||||
SLPH-00020 Imagineer Thunder Pad Transparent
|
||||
SLPH-00021 Imagineer Imagegun
|
||||
SLPH-00022 Optec AI Commander Pro, digital pad with extras / lcd display
|
||||
SLPH-00023 Namco Joystick (SLEH-00004)
|
||||
SLPH-00024 Optec Cockpit Wheel, analog joystick/analog pedals or so
|
||||
SLPH-00025 Optec AI Commander Accessory (extended memo repack ZERO2 version)
|
||||
SLPH-00026 Hori Command Stick PS (SLPH-00026 aka HPS11)
|
||||
SLPH-00027 ASCII Grip, single-handed digital pad (SLEH-00008)
|
||||
SLPH-00028 Hori Grip (gray) (see also: SLPH-00040, and 00086..00088)
|
||||
SLPH-00029 Hori Horipad (clear), digital pad
|
||||
SLPH-00030 Hori Horipad (black), digital pad
|
||||
SLPH-00031 Hori Horipad (gray), digital pad
|
||||
SLPH-00032 Hori Horipad (white), digital pad
|
||||
SLPH-00033 Hori Horipad (blue), digital pad
|
||||
SLPH-00034 Namco G-CON 45, Cinch-based Lightgun (SLEH-0007/SLUH-00035)
|
||||
SLPH-00035 ASCII Fighter stick V Jr. (SLEH-00009)
|
||||
SLPH-00036 Optec Wireless Dual Shot, digital pad with turbo button
|
||||
SLPH-00037 ?
|
||||
SLPH-00038 ASCII Pad V Jr., digital pad without any extras
|
||||
SLPH-00039 ASCII Pad V2 (gray), digital pad with turbo switches (SLEH-00010)
|
||||
SLPH-00040 Hori Grip (black)
|
||||
SLPH-00041 ASCII Grip V
|
||||
SLPH-00042 ASCII Grip V plus (Derby Stallion'99 supplement set), single-hand
|
||||
SLPH-00043 ASCII Pad V2 (clear pink)
|
||||
SLPH-00044 ASCII Pad V2 (clear white)
|
||||
SLPH-00045 ASCII Pad V2 (clear blue)
|
||||
SLPH-00046 ASCII Pad V2 (clear green)
|
||||
SLPH-00047 ASCII Pad V2 (clear black)
|
||||
SLPH-00048 ASCII Pad V2 (clear red/lead?)
|
||||
SLPH-00049 ASCII Pad V2 (clear yellow)
|
||||
SLPH-00050 ASCII Pad V2 (clear orange)
|
||||
SLPH-00051 Taito Streetcar GO! Controller 2 steering "wheel?" tie toe strange
|
||||
SLPH-00052 Koei Video Capture, Ergosoft EGWord, and Lexmark Printer bundle
|
||||
SLPH-00053 Koei Word Processor Ergosoft September EGWORD Ver.2.00
|
||||
SLPH-00054 Hori Zerotech Steering Controller (black)
|
||||
SLPH-00055 Hori Grip (clear blue)
|
||||
SLPH-00056 Hori Grip (clear pink)
|
||||
SLPH-00057 Hori Grip (clear yellow)
|
||||
SLPH-00058 ASCII Pad V2 (gold)
|
||||
SLPH-00059 ASCII Pad V2 (silver)
|
||||
SLPH-00060 ASCII Biohazard, digital pad with re-arranged buttons (SLEH-0011)
|
||||
SLPH-00061 ASCII Pad V2 (pearl white)
|
||||
SLPH-00062 ASCII Pad V2 (pearl blue)
|
||||
SLPH-00063 ASCII Pad V2 (pearl pink)
|
||||
SLPH-00064 ASCII Pad V2 (pearl green)
|
||||
SLPH-00065 ASCII Pad V Pro, with lcd for button-combinations (ASC-0508GX)
|
||||
SLPH-00066 ASCII Arcade Stick 3 "Ultimate"
|
||||
SLPH-00067 ASCII Pad V2 (purple metallic)
|
||||
SLPH-00068 ASCII Pad V2 (lead metallic)
|
||||
SLPH-00069 Namco neGcon (black) (NPC-104), Twist controller (SLEH-0003)
|
||||
SLPH-00070 Sankyo Pachinko FF Controller (alternate to SLPH-00007)
|
||||
SLPH-00071 Hori Command Stick PS Custom
|
||||
SLPH-00072 ASCII Command Pack (memory card add-on or so)
|
||||
SLPH-00073 Optec Wireless digital set (gray) ;\
|
||||
SLPH-00074 Optec Wireless digital set (black) ; pad with receiver
|
||||
SLPH-00075 Optec Wireless digital set (clear) ;
|
||||
SLPH-00076 Optec Wireless digital set (clear blue) ;
|
||||
SLPH-00077 Optec Wireless digital set (clear black) ;/
|
||||
SLPH-00078 Optec Wireless digital shot (gray) ;\
|
||||
SLPH-00079 Optec Wireless digital shot (black) ; extra pad for
|
||||
SLPH-00080 Optec Wireless digital shot (clear) ; second player
|
||||
SLPH-00081 Optec Wireless digital shot (clear blue) ; (without receiver)
|
||||
SLPH-00082 Optec Wireless digital shot (clear black) ;/
|
||||
SLPH-00083 ASCII Stick Justice controller
|
||||
SLPH-00084 Hori ZeroTech Steering Controller (clear)
|
||||
SLPH-00085 Hori Compact joystick (black)
|
||||
SLPH-00086 Hori Compact joystick (clear)
|
||||
SLPH-00087 Hori Compact joystick (clear blue)
|
||||
SLPH-00088 Hori Multi Analog Pad (clear) or Hori Grip (pink?)
|
||||
SLPH-00089 Hori AV Cable with selector
|
||||
SLPH-00090 Hori Multi Analogue Pad (clear black)
|
||||
SLPH-00091 Hori AV Multi-Out Converter
|
||||
SLPH-00092 ASCII Pad V2 (margin green)
|
||||
SLPH-00093 ASCII Pad V2 (margin blue)
|
||||
SLPH-00094 ASCII Pad V2 (margin pink)
|
||||
SLPH-00095 ASCII Pad V2 (margin orange)
|
||||
SLPH-00096 ASCII Hyper Steering V ("high pass tear ring V controller?")
|
||||
SLPH-00097 Hori S Cable with selector (uh, maybe S-video or so?) (HPS-36)
|
||||
SLPH-00098 NSYSCOM Pachinko slot controller (NSC-1)
|
||||
SLPH-00099 ASCII Pad V2 (rainbow)
|
||||
SLPH-00100 ASCII 'Hanging' Fishing Controller, controller for fishing games
|
||||
SLPH-00101 Optec Cockpit big shock
|
||||
SLPH-00102 ASCII Grip V (set for mars story)
|
||||
SLPH-00103 Hori Pad V2 (clear)
|
||||
SLPH-00104 Hori Pad V2 (clear blue)
|
||||
SLPH-00105 Hori Pad V2 (clear pink)
|
||||
SLPH-00106 Hori Pad V2 (black)
|
||||
SLPH-00107 Hori Compact Joystick (camouflage)
|
||||
SLPH-00108 Hori Rumble Digital Pad (clear blue)
|
||||
SLPH-00109 Hori Monoaural AV Cable
|
||||
SLPH-00110 ASCII Pad V2 (marble)
|
||||
SLPH-00111 ASCII Pad V2 (camouflage)
|
||||
SLPH-00112 ASCII Pad V3
|
||||
SLPH-00113 ASCII Pad V3 with cable reel
|
||||
SLPH-00114 ASCII Pad V3 with V2 (pearl white) bundle
|
||||
SLPH-00115 ASCII Pad V3 with V2 (pearl pink) bundle
|
||||
SLPH-00116 ASCII Pad V3 with V2 (pearl blue) bundle
|
||||
SLPH-00117 ASCII Pad V3 (blue) with V2 (pearl green) bundle
|
||||
SLPH-00118 Hori Pad V3
|
||||
SLPH-00119 Hori Pad V3 (white)
|
||||
SLPH-00120 Hori Analog Rumble Pad (clear pink)
|
||||
SLPH-00121 Hori Analog Rumble Pad (clear)
|
||||
SLPH-00122 Hori Analog Rumble Pad (clear blue)
|
||||
SLPH-00123 Hori Analog Rumble Pad (clear red)
|
||||
SLPH-00124 Hori Analog Rumble Pad (clear black)
|
||||
SLPH-00125 Hori Analog Rumble Pad (clear yellow)
|
||||
SLPH-00126 Namco Jogcon, digital pad, steering dial (SLEH-0020/SLUH-00059)
|
||||
SLPH-00127 ?
|
||||
SLPH-00128 ASCII stick ZERO3
|
||||
SLPH-00129 ASCII Pad V2 (wood grain pitch)
|
||||
SLPH-00130 Hori Real Arcade (camouflage)
|
||||
SLPH-00131 Hori Ehrgeiz Stick
|
||||
SLPH-00132 ASCII Pad V3 (blue)
|
||||
SLPH-00133 ASCII Fighter Stick V Jr. (limited edition)
|
||||
SLPH-00134 ASCII Pad V3 (blue) with cable reel
|
||||
SLPH-00135 ASCII Pad V3 (blue) with V2 (silver)
|
||||
SLPH-00136 ASCII Pad V3 with V2 (purple metallic)
|
||||
SLPH-00137 ASCII Pad V3 with V2 (gold)
|
||||
SLPH-00138 ASCII Pad V3 with "VPRO. aka Ascii Fighter Stick V"
|
||||
SLPH-00139 Hori Analog Rumble Pad (gray)
|
||||
SLPH-00140 Hori Analog Rumble Pad (black)
|
||||
SLPH-00141 Hori Analog Rumble Pad (blue)
|
||||
</code></pre>
|
||||
<p>And, maybe unlicensed (they don't have official SLPH numbers, still they are
|
||||
listed as official controllers on PSX CDROM back covers):<br/></p>
|
||||
<pre><code> ASC-05158B ASCII Beatmania Junk (similar to SLEH-0021)
|
||||
ASC-0528T Sammy Shakkato Tambourine
|
||||
BANC-0001 Bandai Fishing Controller
|
||||
BANC-0002 Bandai Kids Station
|
||||
RU017 Konami Dance Dance Revolution Controller (Dance Mat)
|
||||
GAE001 G.A.E. Baton stick with 2 buttons (for The Maestromusic)
|
||||
</code></pre>
|
||||
<p>And whatever:<br/></p>
|
||||
<pre><code> RU029 Konami Beatmania IIDX
|
||||
RU014 Konami Pop'n Music (buttons A,B,C,D,E,F,G,H,I, and Select/Start)
|
||||
RU014-J2 Konami Pop'n Controller 2
|
||||
RU036 Konami Pop'n Controller (Arcade Style)
|
||||
? Produce! Paca Paca Passion
|
||||
? Sega/Ascii Minimoni Shakatto Tambourine
|
||||
</code></pre>
|
||||
<h4 id="sony-licensed-hardware-europe">Sony Licensed Hardware (Europe)</h4>
|
||||
<pre><code> SLEH-00001 Ascii Specialized Pad (similar to SLPH-00005: ASCII ASCIIPAD V)
|
||||
SLEH-00002 Ascii Arcade Stick, psx-shaped digital stick (SLPH-00003)
|
||||
SLEH-00003 Namco Negcon, Twist controller (SLPH-00001)
|
||||
SLEH-00004 Namco Arcade Stick (SLPH-00023)
|
||||
SLEH-00005 Konami Hyper Blaster, IRQ10-based Lightgun (SLPH-00014/SLUH-00017)
|
||||
SLEH-00006 Mad Catz Steering Wheel (SLPH-?)
|
||||
SLEH-00007 Namco G-Con 45, Cinch-based Lightgun (SLPH-00034/SLUH-00035)
|
||||
SLEH-00008 Ascii Grip, single-handed digital pad (SLPH-00027/SLUH-00038)
|
||||
SLEH-00009 Ascii Arcade Stick v2 (SLPH-00035)
|
||||
SLEH-00010 Ascii Enhanced Control Pad (similar as SLEH-00001) (SLPH-00039)
|
||||
SLEH-00011 Resident Evil Pad (aka SLPH-00060 ASCII Biohazard)
|
||||
SLEH-00012 Reality-Quest The Glove (right-handed only) (SLUH-00045/SLPH-?)
|
||||
SLEH-00013 CD Case (small nylon bag for fourteen CDs) (SLPH-?)
|
||||
SLEH-00014 ?
|
||||
SLEH-00015 PlayStation Case (bigger bag for the console) (SLPH-?)
|
||||
SLEH-00016 PlayStation Case + Digital Joypad + Memory Card
|
||||
SLEH-00017 ?
|
||||
SLEH-00018 Ascii Sphere 360 (SLUH-00028/SLPH-?)
|
||||
SLEH-00019 Interact V3 Racing Wheel (SLPH-?)
|
||||
SLEH-00020 Namco JogCon, digital pad, steering dial (SLPH-00126/SLUH-00059)
|
||||
SLEH-00021 Konami Beatmania Controller (SLPH-?)
|
||||
SLEH-00022 ?
|
||||
SLEH-00023 Official Dance Mat (RU017/SLUH-00071) (for PSone and PS2)
|
||||
SLEH-00024 Fanatec Speedster 2 (wheel with pedals) (for PSone and PS2)
|
||||
SLEH-00025 Mad Catz 8MB Memory Card (for PS2)
|
||||
SLEH-00026 Olympus Eye-Trek FMD-20P Game/DVD glasses (for PS2)
|
||||
SLEH-00027 Logitech Cordless Controller... or Eye-Trek FMD-20P, too? (PSx?)
|
||||
SLEH-00028 ?
|
||||
SLEH-00029 Fanatec Speedster 3 (for PS2)
|
||||
SLEH-00030 Logitech Eye Toy (camera?) (for PS2)
|
||||
</code></pre>
|
||||
<p>And, maybe unlicensed:<br/></p>
|
||||
<pre><code> Mad Catz Wrist Rumbler (rumble add-on for pre-dualshock controllers)
|
||||
</code></pre>
|
||||
<h4 id="sony-licensed-hardware-usa">Sony Licensed Hardware (USA)</h4>
|
||||
<pre><code> SLUH-00001 Specialized Joystick (single-axis, digital?)
|
||||
SLUH-00002 Control Pad (redesigned joypad)
|
||||
SLUH-00003 InterAct Piranha Pad, digital pad, autofire/slowmotion
|
||||
SLUH-00017 Konami Justifier, IRQ10-based Lightgun (Hyperblaster/SLPH-00014)
|
||||
SLUH-00018 Enhanced Pad (joypad with whatever extra functions)
|
||||
SLUH-00022 Analog and Digital Steering Wheel with pedals (for testdrive 4?)
|
||||
SLUH-00026 Optec Mach 1 (gray steering/flight controller with pedals)
|
||||
SLUH-00028 Ascii Sphere 360 (SLEH-00018)
|
||||
SLUH-00029 Namco NPC-102 Joystick (single-axis, digital?)
|
||||
SLUH-00031 Interact Program Pad
|
||||
SLUH-00033 Piranha Pad (redesigned joypad)
|
||||
SLUH-00034 NUBY Manufacturing The Heater, white lightgun (irq10 or cinch?)
|
||||
SLUH-00035 Namco G-CON 45, Cinch-based Lightgun (SLEH-0007/SLPH-00034)
|
||||
SLUH-00037 Arcade Stick (single-axis, digital?)
|
||||
SLUH-00038 ASCII Grip V, single-handed digital pad (SLPH-00027/SLEH-00008)
|
||||
SLUH-00040 System Organizer (huh? looks like... a black storage box?)
|
||||
SLUH-00041 V3 Racing Wheel with pedals
|
||||
SLUH-00043 GunCon (bundled with Time Crisis 1)
|
||||
SLUH-00044 Remote Wizard (looks like wireless joypad or so)
|
||||
SLUH-00045 Reality-Quest The Glove (right-handed only) (SLEH-00012/SLPH-?)
|
||||
SLUH-00046 GunCon (bundled with Point Blank)
|
||||
SLUH-00055 Aftershock Wheel with pedals
|
||||
SLUH-00056 UltraRacer Steering Controller (grip-style)
|
||||
SLUH-00057 EA Sports Game Pad (redesigned joypad)
|
||||
SLUH-00058 something for point blank 2 (?) (maybe a lightgun)
|
||||
SLUH-00059 Namco Jogcon, digital pad, steering dial (SLEH-0020/SLPH-00126)
|
||||
SLUH-00061 MadCatz MC2 Racing Wheel (black/gray)
|
||||
SLUH-00063 Bass Landing Fishing Reel controller
|
||||
SLUH-00066 Sportster racing wheel
|
||||
SLUH-00068 Jungle Book Rhythm N Groove Dance Pack
|
||||
SLUH-00071 Konami Dance Pad (DDR Dance Pad) (RU017)
|
||||
SLUH-00072 GunCon (bundled with Point Blank 3)
|
||||
SLUH-00073 GunCon (bundled with Time Crisis 2 - Project Titan)
|
||||
SLUH-00077 Logitech Cordless Controller, analog pad (ps1/ps2)
|
||||
SLUH-00081 Logitech NetPlay Controller, pad with keyboard (usb/ps2)
|
||||
SLUH-00083 Konami Dance Dance Revolution Controller (for PS1 and PS2)
|
||||
SLUH-00084 NYKO iType2, pad with keyboard (usb/ps2)
|
||||
SLUH-00085 Logitech Cordless Action Controller (for PS2)
|
||||
SLUH-00086 Namco/Taiko Drum Master (Taiko Controller Pack) (for PS2)
|
||||
SLUH-00088 RedOctane In the Groove Dance Pad Controller ?
|
||||
SLUH-00090 Dance Pad (bundled with Pump It Up) (for PS2)
|
||||
</code></pre>
|
||||
<h4 id="sony-licensed-hardware-asia">Sony Licensed Hardware (Asia)</h4>
|
||||
<pre><code> Unknown (if any)
|
||||
</code></pre>
|
||||
<h4 id="newer-hardware-add-ons">Newer hardware add-ons?</h4>
|
||||
<pre><code> SCEH-0001 SingStar (USB to Microfon) (for PS2)
|
||||
</code></pre>
|
||||
<h4 id="note">Note</h4>
|
||||
<p>Early SLEH/SLUH devices used 4-digit numbers (eg. the "official" name for
|
||||
SLEH-00003 is SLEH-0003; unlike as shown in the above list).<br/></p>
|
||||
<h4 id="software-cdrom-game-codes">Software (CDROM Game Codes)</h4>
|
||||
<pre><code> SCES-NNNNN Sony Computer Europe Software
|
||||
SCED-NNNNN Sony Computer Europe Demo
|
||||
SLES-NNNNN Sony Licensed Europe Software
|
||||
SLED-NNNNN Sony Licensed Europe Demo
|
||||
SCPS-NNNNN Sony Computer Japan Software
|
||||
SLPS-NNNNN Sony Licensed Japan Software
|
||||
SLPM-NNNNN Sony Licensed Japan ... ?
|
||||
SCUS-NNNNN Sony Computer USA Software
|
||||
SLUS-NNNNN Sony Licensed USA Software
|
||||
PAPX-NNNNN Demo ...?
|
||||
LSP-NNNNNN Lightspan series (non-retail educational games)
|
||||
</code></pre>
|
||||
<p>Note: Multi-disc games have more than one game code. The game code for Disc 1
|
||||
is also printed on the CD cover, and used in memory card filenames. The
|
||||
per-disk game codes are printed on the discs, and are used as boot-executable
|
||||
name in SYSTEM.CNF file. There is no fixed rule for the multi-disc numbering;
|
||||
some games are using increasing numbers of XNNNN or NNNNX (with X increasing
|
||||
from 0 upwards), and some are randomly using values like NNNXX and NNNYY for
|
||||
different discs.<br/></p>
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1F801070h I_STAT - Interrupt status register (R=Status, W=Acknowledge)
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
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|
||||
<h1 id="interrupts">Interrupts</h1>
|
||||
<h4 id="1f801070h-i_stat-interrupt-status-register-rstatus-wacknowledge">1F801070h I_STAT - Interrupt status register (R=Status, W=Acknowledge)</h4>
|
||||
<h4 id="1f801074h-i_mask-interrupt-mask-register-rw">1F801074h I_MASK - Interrupt mask register (R/W)</h4>
|
||||
<p>Status: Read I_STAT (0=No IRQ, 1=IRQ)<br/>
|
||||
Acknowledge: Write I_STAT (0=Clear Bit, 1=No change)<br/>
|
||||
Mask: Read/Write I_MASK (0=Disabled, 1=Enabled)<br/></p>
|
||||
<pre><code> 0 IRQ0 VBLANK (PAL=50Hz, NTSC=60Hz)
|
||||
1 IRQ1 GPU Can be requested via GP0(1Fh) command (rarely used)
|
||||
2 IRQ2 CDROM
|
||||
3 IRQ3 DMA
|
||||
4 IRQ4 TMR0 Timer 0 aka Root Counter 0 (Sysclk or Dotclk)
|
||||
5 IRQ5 TMR1 Timer 1 aka Root Counter 1 (Sysclk or H-blank)
|
||||
6 IRQ6 TMR2 Timer 2 aka Root Counter 2 (Sysclk or Sysclk/8)
|
||||
7 IRQ7 Controller and Memory Card - Byte Received Interrupt
|
||||
8 IRQ8 SIO
|
||||
9 IRQ9 SPU
|
||||
10 IRQ10 Controller - Lightpen Interrupt. Also shared by PIO and DTL cards.
|
||||
11-15 Not used (always zero)
|
||||
16-31 Garbage
|
||||
</code></pre>
|
||||
<h4 id="secondary-irq10-controller-port-1f802030h">Secondary IRQ10 Controller (Port 1F802030h)</h4>
|
||||
<p><a href="../expansionportpio/#exp2-dtl-h2000-io-ports">EXP2 DTL-H2000 I/O Ports</a><br/></p>
|
||||
<h4 id="interrupt-request-execution">Interrupt Request / Execution</h4>
|
||||
<p>The interrupt request bits in I_STAT are edge-triggered, ie. the get set ONLY
|
||||
if the corresponding interrupt source changes from "false to true".<br/>
|
||||
If one or more interrupts are requested and enabled, ie. if "(I_STAT AND
|
||||
I_MASK)=nonzero", then cop0r13.bit10 gets set, and when cop0r12.bit10 and
|
||||
cop0r12.bit0 are set, too, then the interrupt gets executed.<br/></p>
|
||||
<h4 id="interrupt-acknowledge">Interrupt Acknowledge</h4>
|
||||
<p>To acknowledge an interrupt, write a "0" to the corresponding bit in I_STAT.
|
||||
Most interrupts (except IRQ0,4,5,6) must be additionally acknowledged at the
|
||||
I/O port that has caused them (eg. JOY_CTRL.bit4).<br/>
|
||||
Observe that the I_STAT bits are edge-triggered (they get set only on
|
||||
High-to-Low, or False-to-True edges). The correct acknowledge order is:<br/></p>
|
||||
<pre><code> First, acknowledge I_STAT (eg. I_STAT.bit7=0)
|
||||
Then, acknowledge corresponding I/O port (eg. JOY_CTRL.bit4=1)
|
||||
</code></pre>
|
||||
<p>When doing it vice-versa, the hardware may miss further IRQs (eg. when first
|
||||
setting JOY_CTRL.4=1, then a new IRQ may occur in JOY_STAT.4 within a single
|
||||
clock cycle, thereafter, setting I_STAT.7=0 would successfully reset I_STAT.7,
|
||||
but, since JOY_STAT.4 is already set, there'll be no further edge, so I_STAT.7
|
||||
won't be ever set in future).<br/></p>
|
||||
<h4 id="cop0-interrupt-handling">COP0 Interrupt Handling</h4>
|
||||
<p>Relevant COP0 registers are cop0r13 (CAUSE, reason flags), and cop0r12 (SR,
|
||||
control flags), and cop0r14 (EPC, return address), and, cop0cmd=10h (aka RFE
|
||||
opcode) is used to prepare the return from interrupts. For more info, see<br/>
|
||||
<a href="../cpuspecifications/#cop0-exception-handling">COP0 - Exception Handling</a><br/></p>
|
||||
<h4 id="psx-specific-cop0-notes">PSX specific COP0 Notes</h4>
|
||||
<p>COP0 has six hardware interrupt bits, of which, the PSX uses only cop0r13.bit10
|
||||
(the other ones, cop0r13.bit11-15 are always zero). cop0r13.bit10 is NOT a
|
||||
latch, ie. it gets automatically cleared as soon as "(I_STAT AND I_MASK)=zero",
|
||||
so there's no need to do an acknowledge at the cop0 side. COP0 additionally has
|
||||
two software interrupt bits, cop0r13.bit8-9, which do exist in the PSX, too,
|
||||
these bits are read/write-able latches which can be set/cleared manually to
|
||||
request/acknowledge exceptions by software.<br/></p>
|
||||
<h4 id="halt-function-wait-for-interrupt">Halt Function (Wait for Interrupt)</h4>
|
||||
<p>The PSX doesn't have a HALT opcode, so, even if the program is merely waiting
|
||||
for an interrupt to occur, the CPU is always running at full speed, which is
|
||||
resulting in high power consumption, and, in case of emulators, high CPU
|
||||
emulation load. To save energy, and to make emulation smoother on slower
|
||||
computers, I've added a Halt function for use in emulators:<br/>
|
||||
<a href="../expansionportpio/#exp2-nocash-emulation-expansion">EXP2 Nocash Emulation Expansion</a><br/></p>
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||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#interrupt-control">
|
||||
Interrupt Control
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dma-registers">
|
||||
DMA Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#timers-aka-root-counters">
|
||||
Timers (aka Root counters)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cdrom-registers-addressreadwriteindex">
|
||||
CDROM Registers (Address.Read/Write.Index)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#gpu-registers">
|
||||
GPU Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#mdec-registers">
|
||||
MDEC Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-voice-023-registers">
|
||||
SPU Voice 0..23 Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-control-registers">
|
||||
SPU Control Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-reverb-configuration-area">
|
||||
SPU Reverb Configuration Area
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-internal-registers">
|
||||
SPU Internal Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-default-128-bytes-max-8-kbytes">
|
||||
Expansion Region 2 (default 128 bytes, max 8 KBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-dual-serial-port-for-tty-debug-terminal">
|
||||
Expansion Region 2 - Dual Serial Port (for TTY Debug Terminal)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-intdippost">
|
||||
Expansion Region 2 - Int/Dip/Post
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-nocash-emulation-expansion">
|
||||
Expansion Region 2 - Nocash Emulation Expansion
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-3-default-1-byte-max-2-mbytes">
|
||||
Expansion Region 3 (default 1 byte, max 2 MBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#bios-region-default-512-kbytes-max-4-mbytes">
|
||||
BIOS Region (default 512 Kbytes, max 4 MBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#memory-control-3-cache-control">
|
||||
Memory Control 3 (Cache Control)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#coprocessor-registers">
|
||||
Coprocessor Registers
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../graphicsprocessingunitgpu/">
|
||||
Graphics Processing Unit (GPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../geometrytransformationenginegte/">
|
||||
Geometry Transformation Engine (GTE)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../macroblockdecodermdec/">
|
||||
Macroblock Decoder (MDEC)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../soundprocessingunitspu/">
|
||||
Sound Processing Unit (SPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../interrupts/">
|
||||
Interrupts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../dmachannels/">
|
||||
DMA Channels
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../timers/">
|
||||
Timers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromdrive/">
|
||||
CDROM Drive
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../controllersandmemorycards/">
|
||||
Controllers and Memory Cards
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pocketstation/">
|
||||
Pocketstation
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../serialportsio/">
|
||||
Serial Port (SIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../expansionportpio/">
|
||||
Expansion Port (PIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../memorycontrol/">
|
||||
Memory Control
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../unpredictablethings/">
|
||||
Unpredictable Things
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cpuspecifications/">
|
||||
CPU Specifications
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../kernelbios/">
|
||||
Kernel (BIOS)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../arcadecabinets/">
|
||||
Arcade Cabinets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cheatdevices/">
|
||||
Cheat Devices
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../aboutcredits/">
|
||||
About & Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-1">
|
||||
Expansion Region 1
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#scratchpad">
|
||||
Scratchpad
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#memory-control-1">
|
||||
Memory Control 1
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#peripheral-io-ports">
|
||||
Peripheral I/O Ports
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#memory-control-2">
|
||||
Memory Control 2
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#interrupt-control">
|
||||
Interrupt Control
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dma-registers">
|
||||
DMA Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#timers-aka-root-counters">
|
||||
Timers (aka Root counters)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cdrom-registers-addressreadwriteindex">
|
||||
CDROM Registers (Address.Read/Write.Index)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#gpu-registers">
|
||||
GPU Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#mdec-registers">
|
||||
MDEC Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-voice-023-registers">
|
||||
SPU Voice 0..23 Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-control-registers">
|
||||
SPU Control Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-reverb-configuration-area">
|
||||
SPU Reverb Configuration Area
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#spu-internal-registers">
|
||||
SPU Internal Registers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-default-128-bytes-max-8-kbytes">
|
||||
Expansion Region 2 (default 128 bytes, max 8 KBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-dual-serial-port-for-tty-debug-terminal">
|
||||
Expansion Region 2 - Dual Serial Port (for TTY Debug Terminal)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-intdippost">
|
||||
Expansion Region 2 - Int/Dip/Post
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-2-nocash-emulation-expansion">
|
||||
Expansion Region 2 - Nocash Emulation Expansion
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#expansion-region-3-default-1-byte-max-2-mbytes">
|
||||
Expansion Region 3 (default 1 byte, max 2 MBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#bios-region-default-512-kbytes-max-4-mbytes">
|
||||
BIOS Region (default 512 Kbytes, max 4 MBytes)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#memory-control-3-cache-control">
|
||||
Memory Control 3 (Cache Control)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#coprocessor-registers">
|
||||
Coprocessor Registers
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/iomap.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="io-map">I/O Map</h1>
|
||||
<h4 id="expansion-region-1">Expansion Region 1</h4>
|
||||
<pre><code> 1F000000h 80000h Expansion Region (default 512 Kbytes, max 8 MBytes)
|
||||
1F000000h 100h Expansion ROM Header (IDs and Entrypoints)
|
||||
</code></pre>
|
||||
<h4 id="scratchpad">Scratchpad</h4>
|
||||
<pre><code> 1F800000h 400h Scratchpad (1K Fast RAM) (Data Cache mapped to fixed address)
|
||||
</code></pre>
|
||||
<h4 id="memory-control-1">Memory Control 1</h4>
|
||||
<pre><code> 1F801000h 4 Expansion 1 Base Address (usually 1F000000h)
|
||||
1F801004h 4 Expansion 2 Base Address (usually 1F802000h)
|
||||
1F801008h 4 Expansion 1 Delay/Size (usually 0013243Fh; 512Kbytes 8bit-bus)
|
||||
1F80100Ch 4 Expansion 3 Delay/Size (usually 00003022h; 1 byte)
|
||||
1F801010h 4 BIOS ROM Delay/Size (usually 0013243Fh; 512Kbytes 8bit-bus)
|
||||
1F801014h 4 SPU_DELAY Delay/Size (usually 200931E1h)
|
||||
1F801018h 4 CDROM_DELAY Delay/Size (usually 00020843h or 00020943h)
|
||||
1F80101Ch 4 Expansion 2 Delay/Size (usually 00070777h; 128-bytes 8bit-bus)
|
||||
1F801020h 4 COM_DELAY / COMMON_DELAY (00031125h or 0000132Ch or 00001325h)
|
||||
</code></pre>
|
||||
<h4 id="peripheral-io-ports">Peripheral I/O Ports</h4>
|
||||
<pre><code> 1F801040h 1/4 JOY_DATA Joypad/Memory Card Data (R/W)
|
||||
1F801044h 4 JOY_STAT Joypad/Memory Card Status (R)
|
||||
1F801048h 2 JOY_MODE Joypad/Memory Card Mode (R/W)
|
||||
1F80104Ah 2 JOY_CTRL Joypad/Memory Card Control (R/W)
|
||||
1F80104Eh 2 JOY_BAUD Joypad/Memory Card Baudrate (R/W)
|
||||
1F801050h 1/4 SIO_DATA Serial Port Data (R/W)
|
||||
1F801054h 4 SIO_STAT Serial Port Status (R)
|
||||
1F801058h 2 SIO_MODE Serial Port Mode (R/W)
|
||||
1F80105Ah 2 SIO_CTRL Serial Port Control (R/W)
|
||||
1F80105Ch 2 SIO_MISC Serial Port Internal Register (R/W)
|
||||
1F80105Eh 2 SIO_BAUD Serial Port Baudrate (R/W)
|
||||
</code></pre>
|
||||
<h4 id="memory-control-2">Memory Control 2</h4>
|
||||
<pre><code> 1F801060h 4/2 RAM_SIZE (usually 00000B88h; 2MB RAM mirrored in first 8MB)
|
||||
</code></pre>
|
||||
<h4 id="interrupt-control">Interrupt Control</h4>
|
||||
<pre><code> 1F801070h 2 I_STAT - Interrupt status register
|
||||
1F801074h 2 I_MASK - Interrupt mask register
|
||||
</code></pre>
|
||||
<h4 id="dma-registers">DMA Registers</h4>
|
||||
<pre><code> 1F80108xh DMA0 channel 0 - MDECin
|
||||
1F80109xh DMA1 channel 1 - MDECout
|
||||
1F8010Axh DMA2 channel 2 - GPU (lists + image data)
|
||||
1F8010Bxh DMA3 channel 3 - CDROM
|
||||
1F8010Cxh DMA4 channel 4 - SPU
|
||||
1F8010Dxh DMA5 channel 5 - PIO (Expansion Port)
|
||||
1F8010Exh DMA6 channel 6 - OTC (reverse clear OT) (GPU related)
|
||||
1F8010F0h DPCR - DMA Control register
|
||||
1F8010F4h DICR - DMA Interrupt register
|
||||
1F8010F8h unknown
|
||||
1F8010FCh unknown
|
||||
</code></pre>
|
||||
<h4 id="timers-aka-root-counters">Timers (aka Root counters)</h4>
|
||||
<pre><code> 1F80110xh Timer 0 Dotclock
|
||||
1F80111xh Timer 1 Horizontal Retrace
|
||||
1F80112xh Timer 2 1/8 system clock
|
||||
</code></pre>
|
||||
<h4 id="cdrom-registers-addressreadwriteindex">CDROM Registers (Address.Read/Write.Index)</h4>
|
||||
<pre><code> 1F801800h.x.x 1 CD Index/Status Register (Bit0-1 R/W, Bit2-7 Read Only)
|
||||
1F801801h.R.x 1 CD Response Fifo (R) (usually with Index1)
|
||||
1F801802h.R.x 1/2 CD Data Fifo - 8bit/16bit (R) (usually with Index0..1)
|
||||
1F801803h.R.0 1 CD Interrupt Enable Register (R)
|
||||
1F801803h.R.1 1 CD Interrupt Flag Register (R/W)
|
||||
1F801803h.R.2 1 CD Interrupt Enable Register (R) (Mirror)
|
||||
1F801803h.R.3 1 CD Interrupt Flag Register (R/W) (Mirror)
|
||||
1F801801h.W.0 1 CD Command Register (W)
|
||||
1F801802h.W.0 1 CD Parameter Fifo (W)
|
||||
1F801803h.W.0 1 CD Request Register (W)
|
||||
1F801801h.W.1 1 Unknown/unused
|
||||
1F801802h.W.1 1 CD Interrupt Enable Register (W)
|
||||
1F801803h.W.1 1 CD Interrupt Flag Register (R/W)
|
||||
1F801801h.W.2 1 Unknown/unused
|
||||
1F801802h.W.2 1 CD Audio Volume for Left-CD-Out to Left-SPU-Input (W)
|
||||
1F801803h.W.2 1 CD Audio Volume for Left-CD-Out to Right-SPU-Input (W)
|
||||
1F801801h.W.3 1 CD Audio Volume for Right-CD-Out to Right-SPU-Input (W)
|
||||
1F801802h.W.3 1 CD Audio Volume for Right-CD-Out to Left-SPU-Input (W)
|
||||
1F801803h.W.3 1 CD Audio Volume Apply Changes (by writing bit5=1)
|
||||
</code></pre>
|
||||
<h4 id="gpu-registers">GPU Registers</h4>
|
||||
<pre><code> 1F801810h.Write 4 GP0 Send GP0 Commands/Packets (Rendering and VRAM Access)
|
||||
1F801814h.Write 4 GP1 Send GP1 Commands (Display Control)
|
||||
1F801810h.Read 4 GPUREAD Read responses to GP0(C0h) and GP1(10h) commands
|
||||
1F801814h.Read 4 GPUSTAT Read GPU Status Register
|
||||
</code></pre>
|
||||
<h4 id="mdec-registers">MDEC Registers</h4>
|
||||
<pre><code> 1F801820h.Write 4 MDEC Command/Parameter Register (W)
|
||||
1F801820h.Read 4 MDEC Data/Response Register (R)
|
||||
1F801824h.Write 4 MDEC Control/Reset Register (W)
|
||||
1F801824h.Read 4 MDEC Status Register (R)
|
||||
</code></pre>
|
||||
<h4 id="spu-voice-023-registers">SPU Voice 0..23 Registers</h4>
|
||||
<pre><code> 1F801C00h+N*10h 4 Voice 0..23 Volume Left/Right
|
||||
1F801C04h+N*10h 2 Voice 0..23 ADPCM Sample Rate
|
||||
1F801C06h+N*10h 2 Voice 0..23 ADPCM Start Address
|
||||
1F801C08h+N*10h 4 Voice 0..23 ADSR Attack/Decay/Sustain/Release
|
||||
1F801C0Ch+N*10h 2 Voice 0..23 ADSR Current Volume
|
||||
1F801C0Eh+N*10h 2 Voice 0..23 ADPCM Repeat Address
|
||||
</code></pre>
|
||||
<h4 id="spu-control-registers">SPU Control Registers</h4>
|
||||
<pre><code> 1F801D80h 4 Main Volume Left/Right
|
||||
1F801D84h 4 Reverb Output Volume Left/Right
|
||||
1F801D88h 4 Voice 0..23 Key ON (Start Attack/Decay/Sustain) (W)
|
||||
1F801D8Ch 4 Voice 0..23 Key OFF (Start Release) (W)
|
||||
1F801D90h 4 Voice 0..23 Channel FM (pitch lfo) mode (R/W)
|
||||
1F801D94h 4 Voice 0..23 Channel Noise mode (R/W)
|
||||
1F801D98h 4 Voice 0..23 Channel Reverb mode (R/W)
|
||||
1F801D9Ch 4 Voice 0..23 Channel ON/OFF (status) (R)
|
||||
1F801DA0h 2 Unknown? (R) or (W)
|
||||
1F801DA2h 2 Sound RAM Reverb Work Area Start Address
|
||||
1F801DA4h 2 Sound RAM IRQ Address
|
||||
1F801DA6h 2 Sound RAM Data Transfer Address
|
||||
1F801DA8h 2 Sound RAM Data Transfer Fifo
|
||||
1F801DAAh 2 SPU Control Register (SPUCNT)
|
||||
1F801DACh 2 Sound RAM Data Transfer Control
|
||||
1F801DAEh 2 SPU Status Register (SPUSTAT) (R)
|
||||
1F801DB0h 4 CD Volume Left/Right
|
||||
1F801DB4h 4 Extern Volume Left/Right
|
||||
1F801DB8h 4 Current Main Volume Left/Right
|
||||
1F801DBCh 4 Unknown? (R/W)
|
||||
</code></pre>
|
||||
<h4 id="spu-reverb-configuration-area">SPU Reverb Configuration Area</h4>
|
||||
<pre><code> 1F801DC0h 2 dAPF1 Reverb APF Offset 1
|
||||
1F801DC2h 2 dAPF2 Reverb APF Offset 2
|
||||
1F801DC4h 2 vIIR Reverb Reflection Volume 1
|
||||
1F801DC6h 2 vCOMB1 Reverb Comb Volume 1
|
||||
1F801DC8h 2 vCOMB2 Reverb Comb Volume 2
|
||||
1F801DCAh 2 vCOMB3 Reverb Comb Volume 3
|
||||
1F801DCCh 2 vCOMB4 Reverb Comb Volume 4
|
||||
1F801DCEh 2 vWALL Reverb Reflection Volume 2
|
||||
1F801DD0h 2 vAPF1 Reverb APF Volume 1
|
||||
1F801DD2h 2 vAPF2 Reverb APF Volume 2
|
||||
1F801DD4h 4 mSAME Reverb Same Side Reflection Address 1 Left/Right
|
||||
1F801DD8h 4 mCOMB1 Reverb Comb Address 1 Left/Right
|
||||
1F801DDCh 4 mCOMB2 Reverb Comb Address 2 Left/Right
|
||||
1F801DE0h 4 dSAME Reverb Same Side Reflection Address 2 Left/Right
|
||||
1F801DE4h 4 mDIFF Reverb Different Side Reflection Address 1 Left/Right
|
||||
1F801DE8h 4 mCOMB3 Reverb Comb Address 3 Left/Right
|
||||
1F801DECh 4 mCOMB4 Reverb Comb Address 4 Left/Right
|
||||
1F801DF0h 4 dDIFF Reverb Different Side Reflection Address 2 Left/Right
|
||||
1F801DF4h 4 mAPF1 Reverb APF Address 1 Left/Right
|
||||
1F801DF8h 4 mAPF2 Reverb APF Address 2 Left/Right
|
||||
1F801DFCh 4 vIN Reverb Input Volume Left/Right
|
||||
</code></pre>
|
||||
<h4 id="spu-internal-registers">SPU Internal Registers</h4>
|
||||
<pre><code> 1F801E00h+N*04h 4 Voice 0..23 Current Volume Left/Right
|
||||
1F801E60h 20h Unknown? (R/W)
|
||||
1F801E80h 180h Unknown? (Read: FFh-filled) (Unused or Write only?)
|
||||
</code></pre>
|
||||
<h4 id="expansion-region-2-default-128-bytes-max-8-kbytes">Expansion Region 2 (default 128 bytes, max 8 KBytes)</h4>
|
||||
<pre><code> 1F802000h 80h Expansion Region (8bit data bus, crashes on 16bit access?)
|
||||
</code></pre>
|
||||
<h4 id="expansion-region-2-dual-serial-port-for-tty-debug-terminal">Expansion Region 2 - Dual Serial Port (for TTY Debug Terminal)</h4>
|
||||
<pre><code> 1F802020h/1st DUART Mode Register 1.A (R/W)
|
||||
1F802020h/2nd DUART Mode Register 2.A (R/W)
|
||||
1F802021h/Read DUART Status Register A (R)
|
||||
1F802021h/Write DUART Clock Select Register A (W)
|
||||
1F802022h/Read DUART Toggle Baud Rate Generator Test Mode (Read=Strobe)
|
||||
1F802022h/Write DUART Command Register A (W)
|
||||
1F802023h/Read DUART Rx Holding Register A (FIFO) (R)
|
||||
1F802023h/Write DUART Tx Holding Register A (W)
|
||||
1F802024h/Read DUART Input Port Change Register (R)
|
||||
1F802024h/Write DUART Aux. Control Register (W)
|
||||
1F802025h/Read DUART Interrupt Status Register (R)
|
||||
1F802025h/Write DUART Interrupt Mask Register (W)
|
||||
1F802026h/Read DUART Counter/Timer Current Value, Upper/Bit15-8 (R)
|
||||
1F802026h/Write DUART Counter/Timer Reload Value, Upper/Bit15-8 (W)
|
||||
1F802027h/Read DUART Counter/Timer Current Value, Lower/Bit7-0 (R)
|
||||
1F802027h/Write DUART Counter/Timer Reload Value, Lower/Bit7-0 (W)
|
||||
1F802028h/1st DUART Mode Register 1.B (R/W)
|
||||
1F802028h/2nd DUART Mode Register 2.B (R/W)
|
||||
1F802029h/Read DUART Status Register B (R)
|
||||
1F802029h/Write DUART Clock Select Register B (W)
|
||||
1F80202Ah/Read DUART Toggle 1X/16X Test Mode (Read=Strobe)
|
||||
1F80202Ah/Write DUART Command Register B (W)
|
||||
1F80202Bh/Read DUART Rx Holding Register B (FIFO) (R)
|
||||
1F80202Bh/Write DUART Tx Holding Register B (W)
|
||||
1F80202Ch/None DUART Reserved Register (neither R nor W)
|
||||
1F80202Dh/Read DUART Input Port (R)
|
||||
1F80202Dh/Write DUART Output Port Configuration Register (W)
|
||||
1F80202Eh/Read DUART Start Counter Command (Read=Strobe)
|
||||
1F80202Eh/Write DUART Set Output Port Bits Command (Set means Out=LOW)
|
||||
1F80202Fh/Read DUART Stop Counter Command (Read=Strobe)
|
||||
1F80202Fh/Write DUART Reset Output Port Bits Command (Reset means Out=HIGH)
|
||||
</code></pre>
|
||||
<h4 id="expansion-region-2-intdippost">Expansion Region 2 - Int/Dip/Post</h4>
|
||||
<pre><code> 1F802000h 1 DTL-H2000: ATCONS STAT (R)
|
||||
1F802002h 1 DTL-H2000: ATCONS DATA (R and W)
|
||||
1F802004h 2 DTL-H2000: Whatever 16bit data ?
|
||||
1F802030h 1/4 DTL-H2000: Secondary IRQ10 Flags
|
||||
1F802032h 1 DTL-H2000: Whatever IRQ Control ?
|
||||
1F802040h 1 DTL-H2000: Bootmode "Dip switches" (R)
|
||||
1F802041h 1 PSX: POST (external 7 segment display, indicate BIOS boot status)
|
||||
1F802042h 1 DTL-H2000: POST/LED (similar to POST) (other addr, 2-digit wide)
|
||||
1F802070h 1 PS2: POST2 (similar to POST, but PS2 BIOS uses this address)
|
||||
</code></pre>
|
||||
<h4 id="expansion-region-2-nocash-emulation-expansion">Expansion Region 2 - Nocash Emulation Expansion</h4>
|
||||
<pre><code> 1F802060h Emu-Expansion ID1 "E" (R)
|
||||
1F802061h Emu-Expansion ID2 "X" (R)
|
||||
1F802062h Emu-Expansion ID3 "P" (R)
|
||||
1F802063h Emu-Expansion Version (01h) (R)
|
||||
1F802064h Emu-Expansion Enable1 "O" (R/W)
|
||||
1F802065h Emu-Expansion Enable2 "N" (R/W)
|
||||
1F802066h Emu-Expansion Halt (R)
|
||||
1F802067h Emu-Expansion Turbo Mode Flags (R/W)
|
||||
</code></pre>
|
||||
<h4 id="expansion-region-3-default-1-byte-max-2-mbytes">Expansion Region 3 (default 1 byte, max 2 MBytes)</h4>
|
||||
<pre><code> 1FA00000h - Not used by BIOS or any PSX games
|
||||
1FA00000h - POST3 (similar to POST, but PS2 BIOS uses this address)
|
||||
</code></pre>
|
||||
<h4 id="bios-region-default-512-kbytes-max-4-mbytes">BIOS Region (default 512 Kbytes, max 4 MBytes)</h4>
|
||||
<pre><code> 1FC00000h 80000h BIOS ROM (512Kbytes) (Reset Entrypoint at BFC00000h)
|
||||
</code></pre>
|
||||
<h4 id="memory-control-3-cache-control">Memory Control 3 (Cache Control)</h4>
|
||||
<pre><code> FFFE0130h 4 Cache Control
|
||||
</code></pre>
|
||||
<h4 id="coprocessor-registers">Coprocessor Registers</h4>
|
||||
<pre><code> COP0 System Control Coprocessor - 32 registers (not all used)
|
||||
COP1 N/A
|
||||
COP2 Geometry Transformation Engine (GTE) - 64 registers (most are used)
|
||||
COP3 N/A
|
||||
</code></pre>
|
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<input aria-label="Search" autocapitalize="off" autocomplete="off" autocorrect="off" class="md-search__input" data-md-component="search-query" data-md-state="active" name="query" placeholder="Search" required="" spellcheck="false" type="text"/>
|
||||
<label class="md-search__icon md-icon" for="__search">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M9.5 3A6.5 6.5 0 0 1 16 9.5c0 1.61-.59 3.09-1.56 4.23l.27.27h.79l5 5-1.5 1.5-5-5v-.79l-.27-.27A6.516 6.516 0 0 1 9.5 16 6.5 6.5 0 0 1 3 9.5 6.5 6.5 0 0 1 9.5 3m0 2C7 5 5 7 5 9.5S7 14 9.5 14 14 12 14 9.5 12 5 9.5 5z"></path></svg>
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20 11v2H8l5.5 5.5-1.42 1.42L4.16 12l7.92-7.92L13.5 5.5 8 11h12z"></path></svg>
|
||||
</label>
|
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<button aria-label="Clear" class="md-search__icon md-icon" tabindex="-1" type="reset">
|
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M19 6.41 17.59 5 12 10.59 6.41 5 5 6.41 10.59 12 5 17.59 6.41 19 12 13.41 17.59 19 19 17.59 13.41 12 19 6.41z"></path></svg>
|
||||
</button>
|
||||
</form>
|
||||
<div class="md-search__output">
|
||||
<div class="md-search__scrollwrap" data-md-scrollfix="">
|
||||
<div class="md-search-result" data-md-component="search-result">
|
||||
<div class="md-search-result__meta">
|
||||
Initializing search
|
||||
</div>
|
||||
<ol class="md-search-result__list"></ol>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-header__source">
|
||||
<a class="md-source" data-md-component="source" href="https://github.com/psx-spx/psx-spx.github.io/" title="Go to repository">
|
||||
<div class="md-source__icon md-icon">
|
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<svg viewbox="0 0 448 512" xmlns="http://www.w3.org/2000/svg"><path d="M439.55 236.05 244 40.45a28.87 28.87 0 0 0-40.81 0l-40.66 40.63 51.52 51.52c27.06-9.14 52.68 16.77 43.39 43.68l49.66 49.66c34.23-11.8 61.18 31 35.47 56.69-26.49 26.49-70.21-2.87-56-37.34L240.22 199v121.85c25.3 12.54 22.26 41.85 9.08 55a34.34 34.34 0 0 1-48.55 0c-17.57-17.6-11.07-46.91 11.25-56v-123c-20.8-8.51-24.6-30.74-18.64-45L142.57 101 8.45 235.14a28.86 28.86 0 0 0 0 40.81l195.61 195.6a28.86 28.86 0 0 0 40.8 0l194.69-194.69a28.86 28.86 0 0 0 0-40.81z"></path></svg>
|
||||
</div>
|
||||
<div class="md-source__repository">
|
||||
GitHub
|
||||
</div>
|
||||
</a>
|
||||
</div>
|
||||
</nav>
|
||||
</header>
|
||||
<div class="md-container" data-md-component="container">
|
||||
<main class="md-main" data-md-component="main">
|
||||
<div class="md-main__inner md-grid">
|
||||
<div class="md-sidebar md-sidebar--primary" data-md-component="sidebar" data-md-type="navigation">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Navigation" class="md-nav md-nav--primary" data-md-level="0">
|
||||
<label class="md-nav__title" for="__drawer">
|
||||
<a aria-label="PlayStation Specifications - psx-spx" class="md-nav__button md-logo" data-md-component="logo" href=".." title="PlayStation Specifications - psx-spx">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M12 8a3 3 0 0 0 3-3 3 3 0 0 0-3-3 3 3 0 0 0-3 3 3 3 0 0 0 3 3m0 3.54C9.64 9.35 6.5 8 3 8v11c3.5 0 6.64 1.35 9 3.54 2.36-2.19 5.5-3.54 9-3.54V8c-3.5 0-6.64 1.35-9 3.54z"></path></svg>
|
||||
</a>
|
||||
PlayStation Specifications - psx-spx
|
||||
</label>
|
||||
<div class="md-nav__source">
|
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<a class="md-source" data-md-component="source" href="https://github.com/psx-spx/psx-spx.github.io/" title="Go to repository">
|
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<div class="md-source__icon md-icon">
|
||||
<svg viewbox="0 0 448 512" xmlns="http://www.w3.org/2000/svg"><path d="M439.55 236.05 244 40.45a28.87 28.87 0 0 0-40.81 0l-40.66 40.63 51.52 51.52c27.06-9.14 52.68 16.77 43.39 43.68l49.66 49.66c34.23-11.8 61.18 31 35.47 56.69-26.49 26.49-70.21-2.87-56-37.34L240.22 199v121.85c25.3 12.54 22.26 41.85 9.08 55a34.34 34.34 0 0 1-48.55 0c-17.57-17.6-11.07-46.91 11.25-56v-123c-20.8-8.51-24.6-30.74-18.64-45L142.57 101 8.45 235.14a28.86 28.86 0 0 0 0 40.81l195.61 195.6a28.86 28.86 0 0 0 40.8 0l194.69-194.69a28.86 28.86 0 0 0 0-40.81z"></path></svg>
|
||||
</div>
|
||||
<div class="md-source__repository">
|
||||
GitHub
|
||||
</div>
|
||||
</a>
|
||||
</div>
|
||||
<ul class="md-nav__list" data-md-scrollfix="">
|
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<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="..">
|
||||
Home
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../memorymap/">
|
||||
Memory Map
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../iomap/">
|
||||
I/O Map
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../graphicsprocessingunitgpu/">
|
||||
Graphics Processing Unit (GPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../geometrytransformationenginegte/">
|
||||
Geometry Transformation Engine (GTE)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../macroblockdecodermdec/">
|
||||
Macroblock Decoder (MDEC)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../soundprocessingunitspu/">
|
||||
Sound Processing Unit (SPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../interrupts/">
|
||||
Interrupts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../dmachannels/">
|
||||
DMA Channels
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../timers/">
|
||||
Timers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromdrive/">
|
||||
CDROM Drive
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../controllersandmemorycards/">
|
||||
Controllers and Memory Cards
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pocketstation/">
|
||||
Pocketstation
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../serialportsio/">
|
||||
Serial Port (SIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../expansionportpio/">
|
||||
Expansion Port (PIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item md-nav__item--active">
|
||||
<input class="md-nav__toggle md-toggle" data-md-toggle="toc" id="__toc" type="checkbox"/>
|
||||
<label class="md-nav__link md-nav__link--active" for="__toc">
|
||||
Memory Control
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
</label>
|
||||
<a class="md-nav__link md-nav__link--active" href="./">
|
||||
Memory Control
|
||||
</a>
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801000h-expansion-1-base-address-usually-1f000000h">
|
||||
1F801000h - Expansion 1 Base Address (usually 1F000000h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801004h-expansion-2-base-address-usually-1f802000h">
|
||||
1F801004h - Expansion 2 Base Address (usually 1F802000h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801008h-expansion-1-delaysize-usually-0013243fh-512kbytes-8bit-bus">
|
||||
1F801008h - Expansion 1 Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80100ch-expansion-3-delaysize-usually-00003022h-1-byte">
|
||||
1F80100Ch - Expansion 3 Delay/Size (usually 00003022h) (1 byte)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801010h-bios-rom-delaysize-usually-0013243fh-512kbytes-8bit-bus">
|
||||
1F801010h - BIOS ROM Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801014h-spu-delaysize-200931e1h-use-220931e1h-for-spu-ram-reads">
|
||||
1F801014h - SPU Delay/Size (200931E1h) (use 220931E1h for SPU-RAM reads)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801018h-cdrom-delaysize-00020843h-or-00020943h">
|
||||
1F801018h - CDROM Delay/Size (00020843h or 00020943h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80101ch-expansion-2-delaysize-usually-00070777h-128-bytes-8bit-bus">
|
||||
1F80101Ch - Expansion 2 Delay/Size (usually 00070777h) (128 bytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801020h-com_delay-common_delay-00031125h-or-0000132ch-or-00001325h">
|
||||
1F801020h - COM_DELAY / COMMON_DELAY (00031125h or 0000132Ch or 00001325h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801060h-ram_size-rw-usually-00000b88h-or-00000888h">
|
||||
1F801060h - RAM_SIZE (R/W) (usually 00000B88h) (or 00000888h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#fffe0130h-cache-control-rw">
|
||||
FFFE0130h Cache Control (R/W)
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../unpredictablethings/">
|
||||
Unpredictable Things
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cpuspecifications/">
|
||||
CPU Specifications
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../kernelbios/">
|
||||
Kernel (BIOS)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../arcadecabinets/">
|
||||
Arcade Cabinets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cheatdevices/">
|
||||
Cheat Devices
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../aboutcredits/">
|
||||
About & Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801000h-expansion-1-base-address-usually-1f000000h">
|
||||
1F801000h - Expansion 1 Base Address (usually 1F000000h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801004h-expansion-2-base-address-usually-1f802000h">
|
||||
1F801004h - Expansion 2 Base Address (usually 1F802000h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801008h-expansion-1-delaysize-usually-0013243fh-512kbytes-8bit-bus">
|
||||
1F801008h - Expansion 1 Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80100ch-expansion-3-delaysize-usually-00003022h-1-byte">
|
||||
1F80100Ch - Expansion 3 Delay/Size (usually 00003022h) (1 byte)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801010h-bios-rom-delaysize-usually-0013243fh-512kbytes-8bit-bus">
|
||||
1F801010h - BIOS ROM Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801014h-spu-delaysize-200931e1h-use-220931e1h-for-spu-ram-reads">
|
||||
1F801014h - SPU Delay/Size (200931E1h) (use 220931E1h for SPU-RAM reads)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801018h-cdrom-delaysize-00020843h-or-00020943h">
|
||||
1F801018h - CDROM Delay/Size (00020843h or 00020943h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80101ch-expansion-2-delaysize-usually-00070777h-128-bytes-8bit-bus">
|
||||
1F80101Ch - Expansion 2 Delay/Size (usually 00070777h) (128 bytes, 8bit bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801020h-com_delay-common_delay-00031125h-or-0000132ch-or-00001325h">
|
||||
1F801020h - COM_DELAY / COMMON_DELAY (00031125h or 0000132Ch or 00001325h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801060h-ram_size-rw-usually-00000b88h-or-00000888h">
|
||||
1F801060h - RAM_SIZE (R/W) (usually 00000B88h) (or 00000888h)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#fffe0130h-cache-control-rw">
|
||||
FFFE0130h Cache Control (R/W)
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/memorycontrol.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="memory-control">Memory Control</h1>
|
||||
<p>The Memory Control registers are initialized by the BIOS, and, normally
|
||||
software doesn't need to change that settings. Some registers are useful for
|
||||
expansion hardware (allowing to increase the memory size and bus width).<br/></p>
|
||||
<h4 id="1f801000h-expansion-1-base-address-usually-1f000000h">1F801000h - Expansion 1 Base Address (usually 1F000000h)</h4>
|
||||
<h4 id="1f801004h-expansion-2-base-address-usually-1f802000h">1F801004h - Expansion 2 Base Address (usually 1F802000h)</h4>
|
||||
<pre><code> 0-23 Base Address (Read/Write)
|
||||
24-31 Fixed (Read only, always 1Fh)
|
||||
</code></pre>
|
||||
<p>For Expansion 1, the address is forcefully aligned to the selected expansion
|
||||
size (see below), ie. if the size is bigger than 1 byte, then the lower bit(s)
|
||||
of the base address are ignored.<br/>
|
||||
For Expansion 2, trying to use ANY other value than 1F802000h seems to disable
|
||||
the Expansion 2 region, rather than mapping it to the specified address (ie.
|
||||
Port 1F801004h doesn't seem to work).<br/>
|
||||
For Expansion 3, the address seems to be fixed (1FA00000h).<br/></p>
|
||||
<h4 id="1f801008h-expansion-1-delaysize-usually-0013243fh-512kbytes-8bit-bus">1F801008h - Expansion 1 Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)</h4>
|
||||
<h4 id="1f80100ch-expansion-3-delaysize-usually-00003022h-1-byte">1F80100Ch - Expansion 3 Delay/Size (usually 00003022h) (1 byte)</h4>
|
||||
<h4 id="1f801010h-bios-rom-delaysize-usually-0013243fh-512kbytes-8bit-bus">1F801010h - BIOS ROM Delay/Size (usually 0013243Fh) (512Kbytes, 8bit bus)</h4>
|
||||
<h4 id="1f801014h-spu-delaysize-200931e1h-use-220931e1h-for-spu-ram-reads">1F801014h - SPU Delay/Size (200931E1h) (use 220931E1h for SPU-RAM reads)</h4>
|
||||
<h4 id="1f801018h-cdrom-delaysize-00020843h-or-00020943h">1F801018h - CDROM Delay/Size (00020843h or 00020943h)</h4>
|
||||
<h4 id="1f80101ch-expansion-2-delaysize-usually-00070777h-128-bytes-8bit-bus">1F80101Ch - Expansion 2 Delay/Size (usually 00070777h) (128 bytes, 8bit bus)</h4>
|
||||
<pre><code> 0-3 Write Delay (00h..0Fh=01h..10h Cycles)
|
||||
4-7 Read Delay (00h..0Fh=01h..10h Cycles)
|
||||
8 Recovery Period (0=No, 1=Yes, uses COM0 timings)
|
||||
9 Hold Period (0=No, 1=Yes, uses COM1 timings)
|
||||
10 Floating Period (0=No, 1=Yes, uses COM2 timings)
|
||||
11 Pre-strobe Period (0=No, 1=Yes, uses COM3 timings)
|
||||
12 Data Bus-width (0=8bits, 1=16bits)
|
||||
13 Auto Increment (0=No, 1=Yes)
|
||||
14-15 Unknown (R/W)
|
||||
16-20 Memory Window Size (1 SHL N bytes) (0..1Fh = 1 byte ... 2 gigabytes)
|
||||
21-23 Unknown (always zero)
|
||||
24-27 DMA timing override
|
||||
28 Address error flag. Write 1 to it to clear it.
|
||||
29 DMA timing select (0=use normal timings, 1=use bits 24-27)
|
||||
30 Wide DMA (0=use bit 12, 1=override to full 32 bits)
|
||||
31 Wait (1=wait on external device before being ready)
|
||||
</code></pre>
|
||||
<p>When booting, all these registers are using the maximum cycle delays for both
|
||||
reads and writes. Then, the BIOS will immediately select a faster read
|
||||
access delay, resulting in a visible speed up after the first few instructions.
|
||||
The effects aren't immediate however. The BIOS boots using the following instructions:</p>
|
||||
<pre><code class="language-mips">bfc00000 lui $t0, 0x0013
|
||||
bfc00004 ori $t0, 0x243f
|
||||
bfc00008 lui $at, 0x1f80
|
||||
bfc0000c sw $t0, 0x1010($at)
|
||||
bfc00010 nop
|
||||
bfc00014 li $t0, 0x0b88
|
||||
bfc00018 lui $at, 0x1f80
|
||||
bfc0001c sw $t0, 0x1060($at)
|
||||
bfc00020 nop
|
||||
</code></pre>
|
||||
<p>When using a logic analyzer to monitor the boot sequence, the instruction at
|
||||
bfc00014 is still read using the old timings since reset, and then the instruction
|
||||
at bfc00018 is finally read using the sped up timings.</p>
|
||||
<p>Reads and writes access times aren't symmetrical, and are each controlled with
|
||||
their own values. By default, EXP1 will be set to 16 cycles when writing, which
|
||||
is the slowest possible. If the programmer wants to write to a flash chip on
|
||||
EXP1, or communicate with a computer, speeding up write access is recommended.</p>
|
||||
<p>The fastest a port could go would be by setting the lowest 16 bits to zero, which
|
||||
will result in 3 CPU cycles for a single byte access.</p>
|
||||
<p>!CS always goes active at least one cycle before !WR or !RD go active. The various
|
||||
timing changes are between all the events inside the data read/write waveform. The
|
||||
whole formula for computing the total access time is fairly complex overall, and
|
||||
difficult to properly describe.</p>
|
||||
<ul>
|
||||
<li>The pre-strobe period will add delays between the moment the data bus is set,
|
||||
and the moment !CS goes active.</li>
|
||||
<li>The hold period will keep the data in the data bus for some more cycles after
|
||||
!WR goes inactive, and before !CS goes inactive. The accessed device is supposed
|
||||
to sample the data bus during this interval.</li>
|
||||
<li>The floating period will keep the data bus floating for some more cycles after
|
||||
!RD goes inactive, and before !CS goes inactive. The accessed device is supposed
|
||||
to stop driving the data bus during this interval. The CPU will sample the data
|
||||
bus somewhere before or exactly when !CS goes inactive.</li>
|
||||
<li>The recovery period will add delays between two operations.</li>
|
||||
</ul>
|
||||
<p>The data bus width will influence if the CPU does full 16 bits reads, or only
|
||||
8 bits. When doing 32 bits operations, the CPU will issue 2 16-bits operations,
|
||||
or 4 8-bits operations, keeping !CS active the whole time, and strobing !WR or
|
||||
!RD accordingly. When doing these sequences, the address bus will also increment
|
||||
automatically between each operation, if the auto-increment bit is active.</p>
|
||||
<p>This means it is possible to slightly shorten the read time of 4 bytes off the
|
||||
same address by disabling auto-increment, and reading a full word. The CPU will
|
||||
then read 4 bytes off the same address, and place them all into each byte of
|
||||
the loaded register.</p>
|
||||
<p>The DMA timing override portion will replace the access timing when doing DMA,
|
||||
only if the DMA override flag is set.</p>
|
||||
<p>The Wide DMA flag will enable full 32 bits DMA operations on the bus, by reusing
|
||||
the low 16-bits address signals as the high 16-bits data. This means that if
|
||||
the CPU is doing Wide DMA reads, the low 16-bits of the address bus will become
|
||||
inputs.</p>
|
||||
<p>Trying to access addresses that exceed the selected size causes a bus exception.
|
||||
Maximum size would be Expansion 1 = 17h (8MB), BIOS = 16h (4MB), Expansion 2 =
|
||||
0Dh (8KB), Expansion 3 = 15h (2MB). Trying to select larger sizes would overlap
|
||||
the internal I/O ports, and crash the PSX. The Size bits seem to be ignored for
|
||||
SPU/CDROM. The SPU timings seem to be applied for both the 200h-byte SPU region
|
||||
at 1F801C00h and for the 200h-byte unknown region at 1F801E00h.<br/></p>
|
||||
<h4 id="1f801020h-com_delay-common_delay-00031125h-or-0000132ch-or-00001325h">1F801020h - COM_DELAY / COMMON_DELAY (00031125h or 0000132Ch or 00001325h)</h4>
|
||||
<pre><code> 0-3 COM0 - Recovery period cycles
|
||||
4-7 COM1 - Hold period cycles
|
||||
8-11 COM2 - Floating release cycles
|
||||
12-15 COM3 - Strobe active-going edge delay
|
||||
16-31 Unknown/unused (read: always 0000h)
|
||||
</code></pre>
|
||||
<p>This register contains clock cycle offsets that can be added to the Access Time
|
||||
values in Port 1F801008h..1Ch. Works (somehow) like so:<br/></p>
|
||||
<pre><code> 1ST=0, SEQ=0, MIN=0
|
||||
IF Use_COM0 THEN 1ST=1ST+COM0-1, SEQ=SEQ+COM0-1
|
||||
IF Use_COM2 THEN 1ST=1ST+COM2, SEQ=SEQ+COM2
|
||||
IF Use_COM3 THEN MIN=COM3
|
||||
IF 1ST<6 THEN 1ST=1ST+1 ;(somewhat like so)
|
||||
1ST=1ST+AccessTime+2, SEQ=SEQ+AccessTime+2
|
||||
IF 1ST<(MIN+6) THEN 1ST=(MIN+6)
|
||||
IF SEQ<(MIN+2) THEN SEQ=(MIN+2)
|
||||
</code></pre>
|
||||
<p>The total access time is the sum of First Access, plus any Sequential
|
||||
Access(es), eg. for a 32bit access with 8bit bus: Total=1ST+SEQ+SEQ+SEQ.<br/>
|
||||
If the access is done from code in (uncached) RAM, then 0..4 cycles are added
|
||||
to the Total value (the exact number seems to vary depending on the used COMx
|
||||
values or so).<br/></p>
|
||||
<h4 id="1f801060h-ram_size-rw-usually-00000b88h-or-00000888h">1F801060h - RAM_SIZE (R/W) (usually 00000B88h) (or 00000888h)</h4>
|
||||
<pre><code> 0-2 Unknown (no effect)
|
||||
3 Crashes when zero (except PU-7 and EARLY-PU-8, which <do> set bit3=0)
|
||||
4-6 Unknown (no effect)
|
||||
7 Delay on simultaneous CODE+DATA fetch from RAM (0=None, 1=One Cycle)
|
||||
8 Unknown (no effect) (should be set for 8MB, cleared for 2MB)
|
||||
9-11 Define 8MB Memory Window (first 8MB of KUSEG,KSEG0,KSEG1)
|
||||
12-15 Unknown (no effect)
|
||||
16-31 Unknown (Garbage)
|
||||
</code></pre>
|
||||
<p>Possible values for Bit9-11 are:<br/></p>
|
||||
<pre><code> 0 = 1MB Memory + 7MB Locked
|
||||
1 = 4MB Memory + 4MB Locked
|
||||
2 = 1MB Memory + 1MB HighZ + 6MB Locked
|
||||
3 = 4MB Memory + 4MB HighZ
|
||||
4 = 2MB Memory + 6MB Locked ;<--- would be correct for PSX
|
||||
5 = 8MB Memory ;<--- default by BIOS init
|
||||
6 = 2MB Memory + 2MB HighZ + 4MB Locked ;<-- HighZ = Second /RAS
|
||||
7 = 8MB Memory
|
||||
</code></pre>
|
||||
<p>The BIOS initializes this to setting 5 (8MB) (ie. the 2MB RAM repeated 4 times),
|
||||
although the "correct" would be setting 4 (2MB, plus other 6MB Locked). The
|
||||
remaining memory, after the first 8MB, and up to the Expansion/IO/BIOS region
|
||||
seems to be always Locked.<br/>
|
||||
The HighZ regions are FFh-filled, that even when grounding data lines on the
|
||||
system bus (ie. it is NOT a mirror of the PIO expansion region).<br/>
|
||||
Locked means that the CPU generates an exception when accessing that area.<br/>
|
||||
Note: Wipeout uses a BIOS function that changes RAM_SIZE to 00000888h (ie. with
|
||||
corrected size of 2MB, and with the unknown Bit8 cleared). Gundam Battle
|
||||
Assault 2 does actually use the "8MB" space (with stacktop in mirrored RAM at
|
||||
807FFFxxh).<br/>
|
||||
Clearing bit7 causes many games to hang during CDROM loading on both EARLY-PU-8
|
||||
and LATE-PU-8 (but works on PU-18 through PM-41).<br/></p>
|
||||
<h4 id="fffe0130h-cache-control-rw">FFFE0130h Cache Control (R/W)</h4>
|
||||
<pre><code> 0-2 Unknown (Read/Write) (R/W)
|
||||
3 Scratchpad Enable 1 (0=Disable, 1=Enable when Bit7 is set, too) (R/W)
|
||||
4-5 Unknown (Read/Write) (R/W)
|
||||
6 Unknown (read=always zero) (R) or (W) or unused..?
|
||||
7 Scratchpad Enable 2 (0=Disable, 1=Enable when Bit3 is set, too) (R/W)
|
||||
8 Unknown (R/W)
|
||||
9 Crash (0=Normal, 1=Crash if code-cache enabled) (R/W)
|
||||
10 Unknown (read=always zero) (R) or (W) or unused..?
|
||||
11 Code-Cache Enable (0=Disable, 1=Enable) (R/W)
|
||||
12-31 Unknown (R/W)
|
||||
</code></pre>
|
||||
<p>Used by BIOS to initialize cache (in combination with COP0), like so:<br/></p>
|
||||
<pre><code> Init Cache Step 1:
|
||||
[FFFE0130h]=00000804h, then set cop0_sr=00010000h, then
|
||||
zerofill each FOURTH word at [0000..0FFFh], then set cop0_sr=zero.
|
||||
Init Cache Step 2:
|
||||
[FFFE0130h]=00000800h, then set cop0_sr=00010000h, then
|
||||
zerofill ALL words at [0000h..0FFFh], then set cop0_sr=zero.
|
||||
Finish Initialization:
|
||||
read 8 times 32bit from [A0000000h], then set [FFFE0130h]=0001E988h
|
||||
</code></pre>
|
||||
<p>Note: FFFE0130h is described in LSI's "L64360" datasheet, chapter 14 (and
|
||||
probably also in their LR33300/LR33310 datasheet, if it were available in
|
||||
internet).<br/></p>
|
||||
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Memory Map
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Memory Map
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Additional Memory (not mapped to the CPU bus)
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|
||||
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KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions
|
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||||
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KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions
|
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|
||||
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|
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|
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<article class="md-content__inner md-typeset">
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<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/memorymap.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="memory-map">Memory Map</h1>
|
||||
<h4 id="memory-map_1">Memory Map</h4>
|
||||
<pre><code> KUSEG KSEG0 KSEG1
|
||||
00000000h 80000000h A0000000h 2048K Main RAM (first 64K reserved for BIOS)
|
||||
1F000000h 9F000000h BF000000h 8192K Expansion Region 1 (ROM/RAM)
|
||||
1F800000h 9F800000h -- 1K Scratchpad (D-Cache used as Fast RAM)
|
||||
1F801000h 9F801000h BF801000h 8K I/O Ports
|
||||
1F802000h 9F802000h BF802000h 8K Expansion Region 2 (I/O Ports)
|
||||
1FA00000h 9FA00000h BFA00000h 2048K Expansion Region 3 (SRAM BIOS region for DTL cards)
|
||||
1FC00000h 9FC00000h BFC00000h 512K BIOS ROM (Kernel) (4096K max)
|
||||
FFFE0000h (in KSEG2) 0.5K Internal CPU control registers (Cache Control)
|
||||
</code></pre>
|
||||
<p>Additionally, there are a number of memory mirrors.<br/></p>
|
||||
<h4 id="additional-memory-not-mapped-to-the-cpu-bus">Additional Memory (not mapped to the CPU bus)</h4>
|
||||
<pre><code> 1024K VRAM (Framebuffers, Textures, Palettes) (with 2KB Texture Cache)
|
||||
512K Sound RAM (Capture Buffers, ADPCM Data, Reverb Workspace)
|
||||
0.5K CDROM controller RAM (see CDROM Test commands)
|
||||
16.5K CDROM controller ROM (Firmware and Bootstrap for MC68HC05 cpu)
|
||||
32K CDROM Buffer (IC303) (32Kx8) (BUG: only two sectors accessible?)
|
||||
128K External Memory Card(s) (EEPROMs)
|
||||
</code></pre>
|
||||
<h4 id="kusegkseg0kseg1kseg2-memory-regions">KUSEG,KSEG0,KSEG1,KSEG2 Memory Regions</h4>
|
||||
<pre><code> Address Name i-Cache Write-Queue
|
||||
00000000h KUSEG Yes Yes
|
||||
80000000h KSEG0 Yes Yes
|
||||
A0000000h KSEG1 No No
|
||||
C0000000h KSEG2 (No code) No
|
||||
</code></pre>
|
||||
<p>Kernel Memory: KSEG1 is the normal physical memory (uncached), KSEG0 is a
|
||||
mirror thereof (but with cache enabled). KSEG2 is usually intended to contain
|
||||
virtual kernel memory, but in the PSX it's containing Cache Control hardware registers.<br/>
|
||||
User Memory: KUSEG is intended to contain 2GB virtual memory (on extended MIPS
|
||||
processors), the PSX doesn't support virtual memory, and KUSEG simply contains
|
||||
a mirror of KSEG0/KSEG1 (in the first 512MB) (trying to access memory in the
|
||||
remaining 1.5GB causes an exception).<br/></p>
|
||||
<h4 id="i-cache">i-Cache</h4>
|
||||
<p>The i-Cache can hold 4096 bytes, or 1024 instructions.<br/>
|
||||
It is only active in the cached regions (KUSEG and KSEG0).<br/>
|
||||
There are reportedly some restrictions... not sure there... eventually it is
|
||||
using the LSBs of the address as cache-line number... so, for example, it
|
||||
couldn't simultaneously memorize opcodes at BOTH address 80001234h, AND at
|
||||
address 800F1234h (?)<br/></p>
|
||||
<h4 id="scratchpad">Scratchpad</h4>
|
||||
<p>MIPS CPUs usually have a d-Cache, but, in the PSX, Sony has assigned it as
|
||||
what's referenced as the "Scratchpad", mapped to a fixed memory location at
|
||||
1F800000h..1F8003FFh, ie. it's used as Fast RAM, rather than as cache.<br/>
|
||||
There \<might> be a way to disable that behavior (via Port FFFE0130h or
|
||||
so), but, the Kernel is accessing I/O ports via KUSEG, so activating Data Cache
|
||||
would cause the Kernel to access cached I/O ports.<br/>
|
||||
The purpose of the scratchpad is to have a more flexible cache system available
|
||||
to the programmer. Neither the kernel nor the Sony libraries will try to make use
|
||||
of it, so it is therefore completely up for grabs to the programmer. A good example
|
||||
would be if you were to write a piece of code that's doing a lot of CRC computation,
|
||||
to use the 1KB scratchpad to initially load the CRC lookup tables, which incidentally,
|
||||
is exactly 1KB large. Doing this will relieve SDRAM page changes overhead while reading
|
||||
the data to checksum linearly, while also keeping the whole CRC code in the i-Cache,
|
||||
hence being more optimal than what you'd get with an automatic d-Cache system.</p>
|
||||
<h4 id="memory-mirrors">Memory Mirrors</h4>
|
||||
<p>As described above, the 512Mbyte KUSEG, KSEG0, and KSEG1 regions are mirrors of
|
||||
each other. Additional mirrors within these 512MB regions are:<br/></p>
|
||||
<pre><code> 2MB RAM can be mirrored to the first 8MB (strangely, enabled by default)
|
||||
512K BIOS ROM can be mirrored to the last 4MB (disabled by default)
|
||||
Expansion hardware (if any) may be mirrored within expansion region
|
||||
The seven DMA Control Registers at 1F8010x8h are mirrored to 1F8010xCh
|
||||
</code></pre>
|
||||
<p>The size of the RAM, BIOS, Expansion regions can be configured by software, for
|
||||
Expansion Region it's also possible to change base address, see:<br/>
|
||||
<a href="../memorycontrol/">Memory Control</a><br/>
|
||||
The Scratchpad is mirrored only in KUSEG and KSEG0, but not in KSEG1.<br/></p>
|
||||
<h4 id="memory-exceptions">Memory Exceptions</h4>
|
||||
<pre><code> Memory Error ------> Misalignments
|
||||
(and probably also KSEG access in User mode)
|
||||
Bus Error ------> Unused Memory Regions (including Gaps in I/O Region)
|
||||
(unless RAM/BIOS/Expansion mirrors are mapped to "unused" area)
|
||||
</code></pre>
|
||||
<h4 id="write-queue">Write queue</h4>
|
||||
<p>The MIPS CPU has a 4-words deep pass-through write queue, in order to relieve
|
||||
some bus contention when writing to memory. If reading the same memory location
|
||||
that just got written into the write queue, it will first be flushed before
|
||||
being read back from memory.<br/>
|
||||
It is important to realize that the write queue's mechanism is only viable for
|
||||
normal memory attached to the main CPU, and that any hardware register state machine
|
||||
will get messed up by it.<br/>
|
||||
The typical example is the typical JEDEC standard to access flash, which usually does
|
||||
the following sequence to read the ID of a flash chip:</p>
|
||||
<pre><code class="language-C"> base[0xAAA] = 0xAA;
|
||||
base[0x555] = 0x55;
|
||||
base[0xAAA] = 0x90;
|
||||
uint8_t mnfctrID = base[0x000];
|
||||
uint8_t deviceId = base[0x002];
|
||||
</code></pre>
|
||||
<p>In this example above, if <code>base</code> is located in a memory segment that has the write queue
|
||||
enabled, even if the low level assembly code will do the first 3 stores before doing 2 loads,
|
||||
the physical signals sent to that device through the CPU bus will be seen in the sequence:</p>
|
||||
<pre><code>store(0xaaa, 0xaa)
|
||||
load(0x000)
|
||||
store(0x555, 0x55)
|
||||
load(0x002)
|
||||
store(0xaaa, 0x90)
|
||||
</code></pre>
|
||||
<p>Therefore, using KSEG1 that disables the write queue is the only way to ensure that the
|
||||
operations are done in the proper way.</p>
|
||||
<p>The above is valid for most of the hardware connected to the main CPU, such as the CDROM
|
||||
controller, exp1, exp2, the SPU, or the GPU. Therefore, using BF80180xh to access the
|
||||
CDROM registers is more correct than using 1F80180xh.</p>
|
||||
<p>It is noteworthy that the Sony code will still incorrectly use KUSEG as the memory map
|
||||
for all hardware registers, and they then spend a lot of time writing 4 dummy values
|
||||
somewhere, in order to ensure the write queue has been flushed.</p>
|
||||
<p>The SN debugger in contrast is properly using the KSEG1 memory map for all the hardware
|
||||
registers, nullifying the need to flush the write queue when accessing it.</p>
|
||||
<p>It's also noteworthy that doing ANY KSEG1 access (read OR write) will automatically stall
|
||||
the CPU in order to flush the whole write queue before proceeding with the operation.
|
||||
Therefore, all BIOS ROM operations will naturally and effectively have the write queue
|
||||
disabled, as this code requires the CPU to read from KSEG1 constantly.</p>
|
||||
<p>This also means that if using KUSEG for the hardware registers, another method to flush
|
||||
the write queue, albeit potentially slightly less efficient, would be to simply read
|
||||
the first byte located at BFC00000h. The latter is what is effectively described as the
|
||||
official method to flush the write queue in the MIPS handbook. This could be potentially
|
||||
useful to flush the write queue all at once, instead of flushing it word by word.</p>
|
||||
<h4 id="more-memory-info">More Memory Info</h4>
|
||||
<p>For Info on Exception vectors, Unused/Garbage memory locations, I/O Ports,
|
||||
Expansion ROM Headers, and Memory Waitstate Control, etc. see:<br/>
|
||||
<a href="../iomap/">I/O Map</a><br/>
|
||||
<a href="../memorycontrol/">Memory Control</a><br/>
|
||||
<a href="../expansionportpio/#exp1-expansion-rom-header">EXP1 Expansion ROM Header</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-map">BIOS Memory Map</a><br/>
|
||||
<a href="../kernelbios/#bios-memory-allocation">BIOS Memory Allocation</a><br/>
|
||||
<a href="../cpuspecifications/#cop0-exception-handling">COP0 - Exception Handling</a><br/>
|
||||
<a href="../unpredictablethings/">Unpredictable Things</a><br/></p>
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<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M12 8a3 3 0 0 0 3-3 3 3 0 0 0-3-3 3 3 0 0 0-3 3 3 3 0 0 0 3 3m0 3.54C9.64 9.35 6.5 8 3 8v11c3.5 0 6.64 1.35 9 3.54 2.36-2.19 5.5-3.54 9-3.54V8c-3.5 0-6.64 1.35-9 3.54z"></path></svg>
|
||||
</a>
|
||||
PlayStation Specifications - psx-spx
|
||||
</label>
|
||||
<div class="md-nav__source">
|
||||
<a class="md-source" data-md-component="source" href="https://github.com/psx-spx/psx-spx.github.io/" title="Go to repository">
|
||||
<div class="md-source__icon md-icon">
|
||||
<svg viewbox="0 0 448 512" xmlns="http://www.w3.org/2000/svg"><path d="M439.55 236.05 244 40.45a28.87 28.87 0 0 0-40.81 0l-40.66 40.63 51.52 51.52c27.06-9.14 52.68 16.77 43.39 43.68l49.66 49.66c34.23-11.8 61.18 31 35.47 56.69-26.49 26.49-70.21-2.87-56-37.34L240.22 199v121.85c25.3 12.54 22.26 41.85 9.08 55a34.34 34.34 0 0 1-48.55 0c-17.57-17.6-11.07-46.91 11.25-56v-123c-20.8-8.51-24.6-30.74-18.64-45L142.57 101 8.45 235.14a28.86 28.86 0 0 0 0 40.81l195.61 195.6a28.86 28.86 0 0 0 40.8 0l194.69-194.69a28.86 28.86 0 0 0 0-40.81z"></path></svg>
|
||||
</div>
|
||||
<div class="md-source__repository">
|
||||
GitHub
|
||||
</div>
|
||||
</a>
|
||||
</div>
|
||||
<ul class="md-nav__list" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="..">
|
||||
Home
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../memorymap/">
|
||||
Memory Map
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../iomap/">
|
||||
I/O Map
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../graphicsprocessingunitgpu/">
|
||||
Graphics Processing Unit (GPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../geometrytransformationenginegte/">
|
||||
Geometry Transformation Engine (GTE)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../macroblockdecodermdec/">
|
||||
Macroblock Decoder (MDEC)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../soundprocessingunitspu/">
|
||||
Sound Processing Unit (SPU)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../interrupts/">
|
||||
Interrupts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../dmachannels/">
|
||||
DMA Channels
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../timers/">
|
||||
Timers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromdrive/">
|
||||
CDROM Drive
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../controllersandmemorycards/">
|
||||
Controllers and Memory Cards
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pocketstation/">
|
||||
Pocketstation
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../serialportsio/">
|
||||
Serial Port (SIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../expansionportpio/">
|
||||
Expansion Port (PIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../memorycontrol/">
|
||||
Memory Control
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../unpredictablethings/">
|
||||
Unpredictable Things
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cpuspecifications/">
|
||||
CPU Specifications
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../kernelbios/">
|
||||
Kernel (BIOS)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../arcadecabinets/">
|
||||
Arcade Cabinets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cheatdevices/">
|
||||
Cheat Devices
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item md-nav__item--active">
|
||||
<input class="md-nav__toggle md-toggle" data-md-toggle="toc" id="__toc" type="checkbox"/>
|
||||
<label class="md-nav__link md-nav__link--active" for="__toc">
|
||||
PSX Dev-Board Chipsets
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
</label>
|
||||
<a class="md-nav__link md-nav__link--active" href="./">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2000-cpu-board">
|
||||
Sony DTL-H2000 CPU Board
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2000-pio-board">
|
||||
Sony DTL-H2000 PIO Board
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2500-dev-board-pci-bus">
|
||||
Sony DTL-H2500 Dev board (PCI bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2700-dev-board-isa-bus-cpu-analyzer">
|
||||
Sony DTL-H2700 Dev board (ISA bus) (CPU, ANALYZER ...?)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h201a-dt-hv-graphic-artist-board-ibm-pcats-to-ntsc-video">
|
||||
Sony DTL-H201A / DT-HV - Graphic Artist Board (IBM PC/ATs to NTSC video)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dtl-s2020-aka-psy-q-cd-emu">
|
||||
DTL-S2020 aka Psy-Q CD Emu
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psy-q-development-system-psygnosis-1994">
|
||||
PSY-Q Development System (Psygnosis 1994)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h800-sound-artist-board-with-optical-fibre-audio-out">
|
||||
Sony DTL-H800 Sound Artist Board (with optical fibre audio out)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-coh-2000-unknown-purpose">
|
||||
Sony COH-2000 (unknown purpose)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2010-black-external-cdrom-drive-for-dtl-h2000-cd-r-compatible">
|
||||
Sony DTL-H2010 (Black External CDROM Drive for DTL-H2000, CD-R compatible)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2510-gray-internal-cdrom-drive">
|
||||
Sony DTL-H2510 (Gray Internal CDROM Drive)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-scph-9903-gray-scex-free-playstation">
|
||||
Sony SCPH-9903 (Gray SCEx-free Playstation)
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../aboutcredits/">
|
||||
About & Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2000-cpu-board">
|
||||
Sony DTL-H2000 CPU Board
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2000-pio-board">
|
||||
Sony DTL-H2000 PIO Board
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2500-dev-board-pci-bus">
|
||||
Sony DTL-H2500 Dev board (PCI bus)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2700-dev-board-isa-bus-cpu-analyzer">
|
||||
Sony DTL-H2700 Dev board (ISA bus) (CPU, ANALYZER ...?)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h201a-dt-hv-graphic-artist-board-ibm-pcats-to-ntsc-video">
|
||||
Sony DTL-H201A / DT-HV - Graphic Artist Board (IBM PC/ATs to NTSC video)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#dtl-s2020-aka-psy-q-cd-emu">
|
||||
DTL-S2020 aka Psy-Q CD Emu
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psy-q-development-system-psygnosis-1994">
|
||||
PSY-Q Development System (Psygnosis 1994)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h800-sound-artist-board-with-optical-fibre-audio-out">
|
||||
Sony DTL-H800 Sound Artist Board (with optical fibre audio out)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-coh-2000-unknown-purpose">
|
||||
Sony COH-2000 (unknown purpose)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2010-black-external-cdrom-drive-for-dtl-h2000-cd-r-compatible">
|
||||
Sony DTL-H2010 (Black External CDROM Drive for DTL-H2000, CD-R compatible)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-dtl-h2510-gray-internal-cdrom-drive">
|
||||
Sony DTL-H2510 (Gray Internal CDROM Drive)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sony-scph-9903-gray-scex-free-playstation">
|
||||
Sony SCPH-9903 (Gray SCEx-free Playstation)
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/psxdevboardchipsets.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="psx-dev-board-chipsets">PSX Dev-Board Chipsets</h1>
|
||||
<h4 id="sony-dtl-h2000-cpu-board">Sony DTL-H2000 CPU Board</h4>
|
||||
<pre><code> CL825 20pin pin test points (2x10 pins)
|
||||
CL827 20pin pin test points (2x10 pins)
|
||||
U83 64pin SEC KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
U84 64pin SEC KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
CL828 20pin pin test points (2x10 pins)
|
||||
CL826 20pin pin test points (2x10 pins)
|
||||
X10 4pin JC53.20 (PAL, 53.203425MHz)
|
||||
X2 4pin 53.69317MHz (NTSC, 53.693175MHz)
|
||||
U62 20pin LVT244 (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U27 64pin Sony CXD2923AR ;GPU'b
|
||||
CL813 20pin pin test points (2x10 pins)
|
||||
CL814 20pin pin test points (2x10 pins) (with one resistor or so installed)
|
||||
U16 160pin Sony CXD8514Q ;GPU'a
|
||||
X7 4pin 67.73760 MHz
|
||||
CL807 20pin pin test points (2x10 pins)
|
||||
CL809 20pin pin test points (2x10 pins)
|
||||
CL811 20pin pin test points (2x10 pins)
|
||||
U801 208pin Sony CXD8530BQ ;CPU
|
||||
U11 28pin SEC KM48V2104AJ-6 (DRAM 2Mx8) ;Main RAM
|
||||
U10 28pin SEC KM48V2104AJ-6 (DRAM 2Mx8) ;Main RAM
|
||||
U9 28pin SEC KM48V2104AJ-6 (DRAM 2Mx8) ;Main RAM
|
||||
U8 28pin SEC KM48V2104AJ-6 (DRAM 2Mx8) ;Main RAM
|
||||
CN801 100pin Blue connector (to other ISA board)
|
||||
U66 48pin LVT16244? (quad 4-bit 3-state noninverting buffer/line driver)
|
||||
U65 48pin LVT16244? (quad 4-bit 3-state noninverting buffer/line driver)
|
||||
U64 48pin LVT16245? (dual 8-bit 3-state noninverting bus transceiver)
|
||||
U34 100pin Sony CXD2922Q ;SPU
|
||||
U63 14pin 74F74N (dual flipflop)
|
||||
U32 44pin SEC KM416V256B1-8 (DRAM 256Kx16) ;SoundRAM
|
||||
CL801 20pin pin test points (2x10 pins)
|
||||
CL802 20pin pin test points (2x10 pins)
|
||||
Q881 3pin voltage stuff?
|
||||
U31 20pin 74ACT244P (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U35 18pin Sony CXD2554P or OKI M6538-01 (aka MSM6538-01?) (audio related?)
|
||||
U36 20pin Sanyo LC78815 ;16bit D/A Converter
|
||||
U37 8pin NEC ...? C4558C? D426N0B or 9426HOB or so?
|
||||
J806 8pin solder pads...
|
||||
J805 9pin solder pads...
|
||||
J804 10pin solder pads... (11pins, with only 10 contacts?)
|
||||
- 48pin solder pads (12x4pin config jumpers or so)
|
||||
U26 20pin SN74ALSxxx logic?
|
||||
U71 24pin Sony CXA1xxxx? ;RGB?
|
||||
JPxx 9pin PAL/NTSC Jumpers (three 3pin jumpers)
|
||||
J801 24pin solder pads...
|
||||
J803 9pin rear connector: Serial Port (3.3V) (aka "J308") (DB9) (5+4pin)
|
||||
J802 15pin rear connector: AV Multi-out (5+5+5pin)
|
||||
CN881 98pin ISA Bus Cart-edge (2x31 basic pins, plus 2x18 extended pins)
|
||||
</code></pre>
|
||||
<h4 id="sony-dtl-h2000-pio-board">Sony DTL-H2000 PIO Board</h4>
|
||||
<pre><code> JP72x 68pin Black connector (maybe equivalent to 68pin PSX expansion port?)
|
||||
SWI 5pin solder pads...
|
||||
U371 40pin HN27C4000G-12 (512Kx8 / 256Kx16 EPROM) (sticker: "94/7/27")
|
||||
U370 84pin Altera EPM7160ELC84-12 (sticker: "U730, cntl 1")
|
||||
U3 14pin SN74ALS1004N (hex inverters)
|
||||
U43 44pin Altera EPM7032LC44-10 (sticker: "U43, add 1")
|
||||
U716 28pin Sharp LH5498D-35 (FIFO 2Kx9)
|
||||
U717 28pin Sharp LH5498D-35 (FIFO 2Kx9)
|
||||
U719 28pin Sharp LH5498D-35 (FIFO 2Kx9)
|
||||
U720 28pin Sharp LH5498D-35 (FIFO 2Kx9)
|
||||
U724 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
U722 20pin SN74ALS245AN (8bit tristate noninverting bus transceiver)
|
||||
U47 20pin 74FCT244ATP (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U732 48pin LVT16245? (dual 8-bit 3-state noninverting bus transceiver)
|
||||
U711 20pin SN74ALS244BN (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U712 20pin SN74ALS244BN (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U713 20pin 74HC244AP (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U714 20pin 74HC244AP (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U721 20pin SN74ALS244BN (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U55 14pin SN74ALS08N (quad 2-input AND gates)
|
||||
U726 20pin SN74ALS245AN (8bit tristate noninverting bus transceiver)
|
||||
U715 20pin 74HC244AP (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
JPxx 100pin Blue connector (to other ISA board)
|
||||
U738 20pin LVT244 (SMD) (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U734 32pin KM684000G-7 (SRAM 512Kx8) ;\maybe 1Mbyte EXP3 RAM ?
|
||||
U733 32pin KM684000G-7 (SRAM 512Kx8) ;/
|
||||
U725 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
S700 24pin 12bit DIP switch (select I/O Address bits A15..A4)
|
||||
JP700 8pin Jumper (4x2 pins) (select IRQ15/IRQ12/IRQ11/IRQ10)
|
||||
JP7xx 12pin Jumper (3x4 pins) (select DMA7/DMA6/DMA5)
|
||||
U64 48pin LVT16245? (dual 8-bit 3-state noninverting bus transceiver)
|
||||
U65 48pin LVT16244? (quad 4-bit 3-state noninverting buffer/line driver)
|
||||
U66 48pin LVT16244? (quad 4-bit 3-state noninverting buffer/line driver)
|
||||
U737 48pin LVT16244? (quad 4-bit 3-state noninverting buffer/line driver)
|
||||
U710 20pin SN74ALS244BN (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U709 20pin HD74HC245P (8bit tristate noninverting bus transceiver)
|
||||
U723 14pin SN74ALS38AN (quad open-collector NAND gates with buffered output)
|
||||
U2 14pin SN74LS19AN (hex inverters with schmitt-trigger)
|
||||
U1 8pin Dallas DS1232 (MicroMonitor Chip) ;power-good-detect ?
|
||||
U708 20pin HD74HC245P (8bit tristate noninverting bus transceiver)
|
||||
X3 2pin 4.1900 (4.19MHz for SPC700 CPU)
|
||||
U42 80pin P823, U01Q (Sony CXP82300 SPC700 CPU with piggyback EPROM socket)
|
||||
U42' 32pin 27C256A-15 (EPROM 32Kx8) (sticker: "94/11/28")
|
||||
U706 10pin some slim chip with 1x10 pins
|
||||
BT700 2pin battery (or super-cap?) for DS1302S (?) (not installed)
|
||||
U729? 5pin voltage stuff?
|
||||
U40 8pin Dallas DS1302S (real time clock)
|
||||
X4 2pin small crystal (32.768kHz for DS1302S)
|
||||
JP702 34pin Black connector (maybe for internal CDROM Emulator ISA cart?)
|
||||
U736 28pin Sony CXK58257ASP-70L (SRAM 32Kx8) ;CDROM Sector Buffer?
|
||||
U735 100pin Sony CXD1199BQ ;CDROM Decoder/FIFO
|
||||
JP715 40pin Blue connector... to external DTL-H2010 CDROM drive?
|
||||
JP721 9pin rear connector: Joypad/Memcard 2 (DB9)
|
||||
JP719 9pin rear connector: Joypad/Memcard 1 (DB9)
|
||||
? - rear hole for cdrom-cable to Blue 40pin connector?
|
||||
J70x 98pin ISA Bus Cart-edge (2x31 basic pins, plus 2x18 extended pins)
|
||||
</code></pre>
|
||||
<p>JP715 must be either connected to an external CDROM drive, or to some of
|
||||
"terminator" plug (which shortcuts Pin23 and Pin26 with each other; software
|
||||
may hang upon certain I/O operations without that terminator).<br/></p>
|
||||
<h4 id="sony-dtl-h2500-dev-board-pci-bus">Sony DTL-H2500 Dev board (PCI bus)</h4>
|
||||
<p>Newer revision of the DTL-H2000 board. Consists of a single PCI card (plus tiny
|
||||
daughterboard with Controller ports).<br/></p>
|
||||
<pre><code> Mainboard "PI-27 1-589-867-11, DTL-H2500, MAIN BOARD 1575E01A0, SONY"
|
||||
Daughterboard "SONY,CN-102 1-589-865-11,CONNECTOR BOARD,DTL-H2500,1575E02A0"
|
||||
CJ1 9pin rear connector: DB9
|
||||
CJ2? 15pin rear connector: AV Multi-out (5+5+5pin)
|
||||
CJ3 10pin gray connector (to controller daughterboard with two DB9's)
|
||||
CJ4 34pin black connector (maybe for internal CDROM Emulator ISA cart?)
|
||||
CJ5 50pin black connector (to DTL-H2510, Gray Internal CDROM Drive?)
|
||||
CJ6 68pin black connector (maybe equivalent to 68pin PSX expansion port?)
|
||||
- 124pin PCI bus cart edge connector
|
||||
CJ1' 9pin rear connector: DB9 (CTR1, joypad 1) ;\
|
||||
CJ2' 9pin rear connector: DB9 (CTR2, joypad 2) ; on daughterboard
|
||||
CJ3' 10pin gray ribbon cable (to CJ3 on main board) ;/
|
||||
IC103 208pin Sony CXD8530CQ (CPU)
|
||||
IC106 28pin SEC KM48V2104AT-6 (DRAM 2Mx8)
|
||||
IC107 28pin SEC KM48V2104AT-6 (DRAM 2Mx8)
|
||||
IC108 28pin SEC KM48V2104AT-6 (DRAM 2Mx8)
|
||||
IC109 28pin SEC KM48V2104AT-6 (DRAM 2Mx8)
|
||||
IC201 64pin SEC KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
IC202 64pin SEC KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
IC203 160pin Sony CXD8514Q ;GPU'a
|
||||
IC207 64pin Sony CXD2923AR ;GPU'b
|
||||
IC303 28pin HM62W256LFP-7T (CDROM SRAM 32Kx8) ;on back side
|
||||
IC304 52pin "D 2021, SC430920PB, G64C 185, JSAA9618A" (Sub-CPU) ;on back
|
||||
IC305 100pin Sony CXD1199BQ (CDROM Decoder/FIFO) ;on back side
|
||||
IC308 100pin Sony CXD2922BQ (SPU) ;on back side
|
||||
IC310 44pin SEC KM416V256BLT-7 (DRAM 256Kx16) ;SoundRAM ;on back side
|
||||
IC402 24pin something bigger
|
||||
IC404 8pin something small
|
||||
IC405 8pin something small
|
||||
IC501 24pin Sony CXA1645M (Analog RGB to Composite) ;on back side
|
||||
IC701 4pin "RD, 5B" or so ;on back side
|
||||
IC801 +++pin "ALTERA, FLEX, EPF8820ARC208-3, A9607"
|
||||
IC802 20pin LVT245A <-- ;on back side
|
||||
IC803 52pin "IDT71321, LA35J, S9704P" (2Kx8 dual port SRAM)
|
||||
IC804 20pin LVT244A
|
||||
IC805 8pin something with socket (sticker: "PD3")
|
||||
IC807-2 32pin MX 27C1000MC-90 (PROM) ;\on back side
|
||||
IC808 32pin F 29F040A-90 (FLASH) ;/BIOS on these chip(s) or so?
|
||||
IC901 4pin 37, 69 ;\on back side
|
||||
IC902 4pin 37, 69 ;/
|
||||
ICxxx? 28pin "DALLAS, DS1230Y-100, NONVOLATILE SRAM"
|
||||
U28 20pin LVT244A
|
||||
Z1 20pin LVT244A ;\on back side
|
||||
Z2 20pin LVT245A <-- ;/
|
||||
Z3 20pin LVT244A
|
||||
Z4 20pin LVT244A ;\
|
||||
Z5 20pin LVT245A <-- ; on back side
|
||||
Z6 20pin LVT244A ;/
|
||||
Z7 20pin LVT244A
|
||||
Z8 20pin LVT244A
|
||||
Z9 20pin LVT244A
|
||||
X101 4pin RC67.73, JVC 5L (67.7376MHz oscillator for main cpu)
|
||||
X201 4pin JC53.20, JVC 6A (for GPU, PAL)
|
||||
X202 4pin JC53.69, JVC 6A (for GPU, NTSC)
|
||||
X302 3pin 4.000MHz (for sub-cpu)
|
||||
</code></pre>
|
||||
<h4 id="sony-dtl-h2700-dev-board-isa-bus-cpu-analyzer">Sony DTL-H2700 Dev board (ISA bus) (CPU, ANALYZER ...?)</h4>
|
||||
<p>Another revision of the DTL-H2000/DTL-H2500 boards. Consists of a single ISA
|
||||
card stacked together with two huge daughterboards, and probably additionally
|
||||
having a small connector daughterboard. Exact chipset is unknown (there might
|
||||
be components on both sides of the PCBs, most of them not visible due to the
|
||||
PCB stacking, so taking photos/scans of the PCBs would require advanced
|
||||
techniques with screwdrivers).<br/>
|
||||
Currently the only known chip name is an EPROM (MX 27C1000DC-90, with sticker
|
||||
"Title=DTL-H2700, Ver=1.00, Date=96.12.4, Sum=046B No."). The ISA card is
|
||||
having markings: "SONY HCD MWB-7? MADE IN JAPAN, PA47 1-589-003-01 1642E03A0".<br/>
|
||||
One uncommon feature is an extra connector for a "trigger switch" (foot pedal),
|
||||
which is reportedly used for activating performance analyzer logging.<br/></p>
|
||||
<h4 id="sony-dtl-h201a-dt-hv-graphic-artist-board-ibm-pcats-to-ntsc-video">Sony DTL-H201A / DT-HV - Graphic Artist Board (IBM PC/ATs to NTSC video)</h4>
|
||||
<pre><code> X2 xpin TXC-2 OSC 66.000MHz
|
||||
X1 xpin TXC-2AOSC 53.693MHz
|
||||
U16 14pin 74F74 (dual flipflop)
|
||||
U29 14pin 74AS04 (hex inverters)
|
||||
U14 20pin LVT244 (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U18 20pin LVT244 (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U15 20pin ACT244 (dual 4-bit 3-state noninverting buffer/line driver)
|
||||
U11 84pin Altera EPM7096LC84-12 (sticker: "artpc13" or "ARTPC13")
|
||||
U13 160pin Sony CXD8514Q ;GPU'a
|
||||
U5 14pin ALS38A ? (quad open-collector NAND gates with buffered output)
|
||||
U27 20pin ALS244AJ ? (dual 4bit tristate noninverting buffer/line driver)
|
||||
Q1 3pin T B596
|
||||
U23 64pin KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
U22 64pin KM4216V256G-60 (DRAM 256Kx16) ;dual-ported VRAM
|
||||
U28 64pin Sony CXD2923AR ;GPU'b
|
||||
S1 16pin 8bit DIP switch (select I/O address A15..A8)
|
||||
S2 8pin 4bit DIP switch (select I/O address A7..A4)
|
||||
U1 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
U2 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
U3 20pin ALS245A (8bit tristate noninverting bus transceiver)
|
||||
JP9 12pin Jumper (6x2 pins) (select IRQ15/IRQ11/IRQ10/IRQ9/IRQ5/IRQ3)
|
||||
U26 24pin Sony CXA1145M ? ;RGB?
|
||||
JP10 3pin Jumper ;\
|
||||
JP12 3pin Jumper ; select "S" or "O" (?)
|
||||
JP11 3pin Jumper ;/
|
||||
J3 2pin? Yellow connector (composite video out?)
|
||||
J2? pin? Mini DIN? connector (maybe S-video out?)
|
||||
J1 15pin High Density SubD (maybe video multi out?)
|
||||
CJx 98pin ISA Bus Cart-edge (2x31 basic pins, plus 2x18 extended pins)
|
||||
</code></pre>
|
||||
<h4 id="dtl-s2020-aka-psy-q-cd-emu">DTL-S2020 aka Psy-Q CD Emu</h4>
|
||||
<pre><code> Yellow PCB "CD Emulator System, (C) Cirtech & SN Systems Ldt, 1994 v1.2"
|
||||
IC 24pin GAL20V8B
|
||||
IC 68pin Analog Devices ADSP-2101 (16bit DSP Microprocessor)
|
||||
IC 20pin HD74HC244P
|
||||
IC15 20pin HD74HC244P
|
||||
IC14 20pin CD74HCT245E
|
||||
IC7 28pin 27C512-10 (EPROM 64Kx8) (yellow sticker, without text)
|
||||
IC 28pin HY62256ALP-70 (SRAM 32Kx8)
|
||||
IC12 28pin HY62256ALP-70 (SRAM 32Kx8)
|
||||
IC 28pin HY62256ALP-70 (SRAM 32Kx8)
|
||||
IC13 84pin Emulex/QLogic FAS216 (Fast Architecture SCSI Processor)
|
||||
IC5 84pin Emulex/QLogic FAS216 (Fast Architecture SCSI Processor)
|
||||
IC4 24pin GAL20V8B (near IO Addr jumpers)
|
||||
IC 20pin 74LS244B1 (near lower 8bit of ISA databus)
|
||||
IC 20pin SN74LS245N? (near lower 8bit of ISA databus)
|
||||
IC 20pin SN74LS245N (near upper 8bit of ISA databus)
|
||||
DMA 12pin Jumpers (select DMA7/6/5)
|
||||
IRQ 12pin Jumpers (select IRQ15/12/11/10/7/5)
|
||||
IO 16pin Jumpers (select IO Addr 300/308/310/318/380/388/390/398)
|
||||
SCSI 6pin Jumpers (select SCSI ID 4/2/1) (aka 3bit 0..7 ?)
|
||||
PL3 34pin Connector to DTL-H2000 ?
|
||||
PL1 50pin Connector to INTERNAL SCSI hardware ?
|
||||
PL2 50pin? Connector to EXTERNAL SCSI hardware ? (25pin plug/50pin cable?)
|
||||
Jx 98pin ISA Bus Cart-edge (2x31 basic pins, plus 2x18 extended pins)
|
||||
</code></pre>
|
||||
<p>Note: There's also a similar ISA cart (DTL-S510B) with less chips and less
|
||||
connectors.<br/>
|
||||
Note: The SN Systems carts seem to have been distributed by Sony (with
|
||||
"DTL-Sxxxx" numbers), and also distributed by Psygnosis. The external SCSI
|
||||
connectors can be possibly also used with Psy-Q Development Systems for SNES
|
||||
and Sega Saturn?<br/></p>
|
||||
<h4 id="psy-q-development-system-psygnosis-1994">PSY-Q Development System (Psygnosis 1994)</h4>
|
||||
<pre><code> 32pin GM76C8128ALLFW85 (SRAM 128Kx8)
|
||||
44pin ALTERA EPM7032LC44-15T
|
||||
34pin EMULEX FAS101 (SCSI Interface Processor)
|
||||
28pin 27C64 (EPROM 8Kx8) (green sticker, without text)
|
||||
20pin LCX245 (=74245?)
|
||||
8pin 2112, CPA, H9527 (?)
|
||||
3pin transistor? voltage regulator?
|
||||
20pin DIP socket (containing two 10pin resistor networks)
|
||||
20pin DIP socket (containing two 10pin resistor networks)
|
||||
2pin CR2032 Battery 3V
|
||||
68pin Connector to PSX "Parallel I/O" expansion port
|
||||
25pin Connector to SCSI hardware (to DTL-S510B or DTL-S2020 ISA cart or so?)
|
||||
</code></pre>
|
||||
<h4 id="sony-dtl-h800-sound-artist-board-with-optical-fibre-audio-out">Sony DTL-H800 Sound Artist Board (with optical fibre audio out)</h4>
|
||||
<pre><code> U15 24pin ?
|
||||
U5 28pin 27C256 (EPROM 32Kx8) (not installed)
|
||||
U7 4pin 67.7376MHz oscillator
|
||||
U8 14pin ?
|
||||
U11 44pin SEC KM416V256B1-8 (DRAM 256Kx16) ;SoundRAM
|
||||
(44pin package with middle 4pin missing, 40pins used)
|
||||
U10 100pin Sony CXD2925Q ;SPU
|
||||
U4 160pin Lattice IspLSI 3256 (sticker: "VER3")
|
||||
U6 128pin Lattice IspLSI xxxx ?
|
||||
U12 48pin ?
|
||||
U13 48pin ?
|
||||
U3 20pin 74ACT244
|
||||
U14 5pin "LM25755, -3.3 P+" ?
|
||||
U2 54pin ?
|
||||
U1 54pin ?
|
||||
U9 ?pin GP1F31T (light transmitting unit for optical fibre cable)
|
||||
? 124pin PCI bus cart edge connector
|
||||
? 8pin internal jumper/connector? (7pin installed, 1pin empty)
|
||||
</code></pre>
|
||||
<p>Note: There's also a similar board (DTL-H700) for MAC/NuBus instead of PCI bus.<br/></p>
|
||||
<h4 id="sony-coh-2000-unknown-purpose">Sony COH-2000 (unknown purpose)</h4>
|
||||
<pre><code> U1 14pin SN74ALS388N ?
|
||||
U2 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
U3 20pin SN74ALS688N (8bit inverting identity comparator with enable)
|
||||
U4 24pin PALxxx ?
|
||||
U5 20pin SN74ALS245AN
|
||||
U6 20pin SN74ALS245AN
|
||||
U7 20pin SN74ALS244N
|
||||
U8 20pin SN74ALS244N
|
||||
U9 20pin SN74ALS245AN
|
||||
U10 20pin SN74ALS245AN
|
||||
U11 20pin SN74ALS244N
|
||||
S2 16pin 8bit DIP switch (ISA 15/14/13/12/11/10/9/8) ;I/O address bit15-8
|
||||
S1 8pin 4bit DIP switch (ISA 7/6/5/4) ;I/O address bit7-4
|
||||
S3 8pin 4bit DIP switch (BISO? 3/2/1/0) ;BISO? or BISD? or 8150?
|
||||
JPxx .... several jumpers (unknown purpose)
|
||||
Jx 98pin ISA Bus Cart-edge (2x31 basic pins, plus 2x18 extended pins)
|
||||
J5 68pin Connector on rear side (unknown purpose)
|
||||
</code></pre>
|
||||
<p>Unknown what COH-2000 was used for. One theory was that it's related to
|
||||
PSX-based arcade cabinets. The 68pin connector might be also related to the
|
||||
68pin PSX "Parallel I/O" expansion port.<br/></p>
|
||||
<h4 id="sony-dtl-h2010-black-external-cdrom-drive-for-dtl-h2000-cd-r-compatible">Sony DTL-H2010 (Black External CDROM Drive for DTL-H2000, CD-R compatible)</h4>
|
||||
<p>External front loading CDROM drive with Eject button. Connects to the blue
|
||||
40pin connector on DTL-H2000 boards.<br/></p>
|
||||
<pre><code> IC101 100pin SONY CXD2515Q (Signal Processor + Servo Amp) ;\
|
||||
IC102 28pin BA6297AFP ; on mainboard
|
||||
ICxx 20pin SONY CXA1571N (RF Amp) (on tiny daughtboard) ; (HCMK-81X)
|
||||
CN101 21pin connector to DEX2010.SCH board ;
|
||||
CN10x 12pin connector to KSS-240A (laser pickup) ;
|
||||
S101 2pin pos0 switch or so? ;
|
||||
M101 2pin spindle motor ;/
|
||||
U1 20pin 74ALS244BN ;\
|
||||
U2 20pin 74ALS244BN ;
|
||||
U3 20pin 74ALS244BN ; on DEX2010.SCH board
|
||||
J1 2pin connector to EJECT BUTTON ;
|
||||
J2 5pin connector to LOADING MOTOR ;
|
||||
J3 21pin connector to mainboard ;
|
||||
JP1 40pin external connector to DTL-H2000 ;/
|
||||
CN151 5pin connector to DEX2010.SCH board ;\
|
||||
M151 2pin loading motor (eject motor) ; on CDM 14, CMK PSX board
|
||||
S151 2pin OUT SW ;\switches, probably to ;
|
||||
S152 2pin IN SW ;/sense load/eject status ;/
|
||||
CN1 2pin connector to DEX2010.SCH board ;\on DTL-H2010(1) board
|
||||
SW1 2pin eject button ;/
|
||||
</code></pre>
|
||||
<p>The required cable consists of a Yamaichi NFS-40a female connector (blue
|
||||
connector on DTL-H2000 side), 0.635mm pitch ribbon cable, and 3M Sub-D MDR40
|
||||
connector (silver connector on DTL-H2010 side). But caution: the odd/even pins
|
||||
on the cable are somewhat swapped, on DTL-H2000 side the wires should be
|
||||
ordered 1,2,3,4,..,39,40, but on DTL-H2010 side they should be ordered
|
||||
2,1,4,3,..,40,39.<br/></p>
|
||||
<h4 id="sony-dtl-h2510-gray-internal-cdrom-drive">Sony DTL-H2510 (Gray Internal CDROM Drive)</h4>
|
||||
<p>This is some sort of a mimmicked front loading PC CDROM drive (consisting of a
|
||||
tray that contains a normal (top-loading) PSX cdrom drive unit).<br/></p>
|
||||
<pre><code> IC309 80pin Sony CXD2510Q (CDROM Signal Processor)
|
||||
ICxx ?pin Unknown if there are further ICs (eg. CXA1782BR should exist?)
|
||||
CN1 10pin Connector to daughterboard (with drive unit)
|
||||
CN2 4pin Connector to PC power supply (12V/5V and 2xGND)
|
||||
CN3 50pin Connector to DTL-H2500 or so? (need "PCS-E50FC" plug?)
|
||||
</code></pre>
|
||||
<p>There is no eject button, unknown if there's some eject motor, or if one
|
||||
needs to push/pull the drive tray manually.<br/></p>
|
||||
<h4 id="sony-scph-9903-gray-scex-free-playstation">Sony SCPH-9903 (Gray SCEx-free Playstation)</h4>
|
||||
<p>A rare SCEx-free Playstation that can boot from CDR's without SCEx strings;
|
||||
maybe intended for beta-testers. Marked "Property of Sony Computer
|
||||
Entertainment", "U/C".<br/></p>
|
||||
</article>
|
||||
</div>
|
||||
</div>
|
||||
</main>
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio_baud-notes">
|
||||
SIO_BAUD Notes
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio-ports-vs-joy-ports">
|
||||
SIO Ports vs JOY Ports
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#note">
|
||||
Note
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio-games">
|
||||
SIO Games
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#8251a-note">
|
||||
8251A Note
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../expansionportpio/">
|
||||
Expansion Port (PIO)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../memorycontrol/">
|
||||
Memory Control
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../unpredictablethings/">
|
||||
Unpredictable Things
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cpuspecifications/">
|
||||
CPU Specifications
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../kernelbios/">
|
||||
Kernel (BIOS)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../arcadecabinets/">
|
||||
Arcade Cabinets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cheatdevices/">
|
||||
Cheat Devices
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../aboutcredits/">
|
||||
About & Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
|
||||
<div class="md-sidebar__scrollwrap">
|
||||
<div class="md-sidebar__inner">
|
||||
<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
|
||||
<label class="md-nav__title" for="__toc">
|
||||
<span class="md-nav__icon md-icon"></span>
|
||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801050h-sio_tx_data-w">
|
||||
1F801050h SIO_TX_DATA (W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801050h-sio_rx_data-r">
|
||||
1F801050h SIO_RX_DATA (R)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801054h-sio_stat-r">
|
||||
1F801054h SIO_STAT (R)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f801058h-sio_mode-rw-eg-004eh-8n1-with-factormul16">
|
||||
1F801058h SIO_MODE (R/W) (eg. 004Eh --> 8N1 with Factor=MUL16)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80105ah-sio_ctrl-rw">
|
||||
1F80105Ah SIO_CTRL (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80105ch-sio_misc-rw">
|
||||
1F80105Ch SIO_MISC (R/W)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#1f80105eh-sio_baud-rw-eg-00dch-9600-bauds-when-factormul16">
|
||||
1F80105Eh SIO_BAUD (R/W) (eg. 00DCh --> 9600 bauds; when Factor=MUL16)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio_tx_data-notes">
|
||||
SIO_TX_DATA Notes
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio_rx_data-notes">
|
||||
SIO_RX_DATA Notes
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#interrupt-acknowledge-notes">
|
||||
Interrupt Acknowledge Notes
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio_baud-notes">
|
||||
SIO_BAUD Notes
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio-ports-vs-joy-ports">
|
||||
SIO Ports vs JOY Ports
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#note">
|
||||
Note
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#sio-games">
|
||||
SIO Games
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#8251a-note">
|
||||
8251A Note
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/serialportsio.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="serial-port-sio">Serial Port (SIO)</h1>
|
||||
<h4 id="1f801050h-sio_tx_data-w">1F801050h SIO_TX_DATA (W)</h4>
|
||||
<pre><code> 0-7 Data to be sent
|
||||
8-31 Not used
|
||||
</code></pre>
|
||||
<p>Writing to this register starts transmit (if, or as soon as, TXEN=1 and CTS=on
|
||||
and SIO_STAT.2=Ready). Writing to this register while SIO_STAT.0=Busy causes
|
||||
the old value to be overwritten.<br/>
|
||||
The "TXEN=1" condition is a bit more complex: Writing to SIO_TX_DATA latches
|
||||
the current TXEN value, and the transfer DOES start if the current TXEN value
|
||||
OR the latched TXEN value is set (ie. if TXEN gets cleared after writing to
|
||||
SIO_TX_DATA, then the transfer may STILL start if the old latched TXEN value
|
||||
was set; this appears for SIO transfers in Wipeout 2097).<br/></p>
|
||||
<h4 id="1f801050h-sio_rx_data-r">1F801050h SIO_RX_DATA (R)</h4>
|
||||
<pre><code> 0-7 Received Data (1st RX FIFO entry) (oldest entry)
|
||||
8-15 Preview (2nd RX FIFO entry)
|
||||
16-23 Preview (3rd RX FIFO entry)
|
||||
24-31 Preview (4th RX FIFO entry) (5th..8th cannot be previewed)
|
||||
</code></pre>
|
||||
<p>A data byte can be read when SIO_STAT.1=1. Data should be read only via 8bit
|
||||
memory access (the 16bit/32bit "preview" feature is rather unusable).<br/></p>
|
||||
<h4 id="1f801054h-sio_stat-r">1F801054h SIO_STAT (R)</h4>
|
||||
<pre><code> 0 TX Ready Flag 1 (1=Ready/Started) (depends on CTS) (TX requires CTS)
|
||||
1 RX FIFO Not Empty (0=Empty, 1=Not Empty)
|
||||
2 TX Ready Flag 2 (1=Ready/Finished) (depends on TXEN and on CTS)
|
||||
3 RX Parity Error (0=No, 1=Error; Wrong Parity, when enabled) (sticky)
|
||||
4 RX FIFO Overrun (0=No, 1=Error; Received more than 8 bytes) (sticky)
|
||||
5 RX Bad Stop Bit (0=No, 1=Error; Bad Stop Bit) (when RXEN) (sticky)
|
||||
6 RX Input Level (0=Normal, 1=Inverted) ;only AFTER receiving Stop Bit
|
||||
7 DSR Input Level (0=Off, 1=On) (remote DTR) ;DSR not required to be on
|
||||
8 CTS Input Level (0=Off, 1=On) (remote RTS) ;CTS required for TX
|
||||
9 Interrupt Request (0=None, 1=IRQ) (sticky)
|
||||
10 Unknown (always zero)
|
||||
11-25 Baudrate Timer (15bit timer, decrementing at 33MHz)
|
||||
26-31 Unknown (usually zero, sometimes all bits set)
|
||||
</code></pre>
|
||||
<p>Note: Bit0 gets cleared after sending the Startbit, Bit2 gets cleared after
|
||||
sending all bits up to including the Stopbit.<br/></p>
|
||||
<h4 id="1f801058h-sio_mode-rw-eg-004eh-8n1-with-factormul16">1F801058h SIO_MODE (R/W) (eg. 004Eh --> 8N1 with Factor=MUL16)</h4>
|
||||
<pre><code> 0-1 Baudrate Reload Factor (1=MUL1, 2=MUL16, 3=MUL64) (or 0=STOP)
|
||||
2-3 Character Length (0=5bits, 1=6bits, 2=7bits, 3=8bits)
|
||||
4 Parity Enable (0=No, 1=Enable)
|
||||
5 Parity Type (0=Even, 1=Odd) (seems to be vice-versa...?)
|
||||
6-7 Stop bit length (0=Reserved/1bit, 1=1bit, 2=1.5bits, 3=2bits)
|
||||
8-15 Not used (always zero)
|
||||
</code></pre>
|
||||
<h4 id="1f80105ah-sio_ctrl-rw">1F80105Ah SIO_CTRL (R/W)</h4>
|
||||
<pre><code> 0 TX Enable (TXEN) (0=Disable, 1=Enable, when CTS=On)
|
||||
1 DTR Output Level (0=Off, 1=On)
|
||||
2 RX Enable (RXEN) (0=Disable, 1=Enable) ;Disable also clears RXFIFO
|
||||
3 TX Output Level (0=Normal, 1=Inverted, during Inactivity & Stop bits)
|
||||
4 Acknowledge (0=No change, 1=Reset SIO_STAT.Bits 3,4,5,9) (W)
|
||||
5 RTS Output Level (0=Off, 1=On)
|
||||
6 Reset (0=No change, 1=Reset most SIO_registers to zero) (W)
|
||||
7 Unknown? (read/write-able when FACTOR non-zero) (otherwise always zero)
|
||||
8-9 RX Interrupt Mode (0..3 = IRQ when RX FIFO contains 1,2,4,8 bytes)
|
||||
10 TX Interrupt Enable (0=Disable, 1=Enable) ;when SIO_STAT.0-or-2 ;Ready
|
||||
11 RX Interrupt Enable (0=Disable, 1=Enable) ;when N bytes in RX FIFO
|
||||
12 DSR Interrupt Enable (0=Disable, 1=Enable) ;when SIO_STAT.7 ;DSR=On
|
||||
13-15 Not used (always zero)
|
||||
</code></pre>
|
||||
<h4 id="1f80105ch-sio_misc-rw">1F80105Ch SIO_MISC (R/W)</h4>
|
||||
<p>This is an internal register, which usually shouldn't be accessed by software.
|
||||
Messing with it has rather strange effects: After writing a value "X" to this
|
||||
register, reading returns "X ROR 8" eventually "ANDed with 1F1Fh and ORed with
|
||||
C0C0h or 8080h" (depending on the character length in SIO_MODE).<br/></p>
|
||||
<h4 id="1f80105eh-sio_baud-rw-eg-00dch-9600-bauds-when-factormul16">1F80105Eh SIO_BAUD (R/W) (eg. 00DCh --> 9600 bauds; when Factor=MUL16)</h4>
|
||||
<pre><code> 0-15 Baudrate Reload value for decrementing Baudrate Timer
|
||||
</code></pre>
|
||||
<p>The Baudrate is calculated (based on SIO_BAUD, and on Factor in SIO_MODE):<br/></p>
|
||||
<pre><code> BitsPerSecond = (44100Hz*300h) / MIN(((Reload*Factor) AND NOT 1),Factor)
|
||||
</code></pre>
|
||||
<h4 id="sio_tx_data-notes">SIO_TX_DATA Notes</h4>
|
||||
<p>The hardware can hold (almost) 2 bytes in the TX direction (one being currently
|
||||
transferred, and, once when the start bit was sent, another byte can be stored
|
||||
in SIO_TX_DATA). When writing to SIO_TX_DATA, both SIO_STAT.0 and SIO_STAT.2
|
||||
become zero. As soon as the transfer starts, SIO_STAT.0 becomes set (indicating
|
||||
that one can write a new byte to SIO_TX_DATA; although the transmission is
|
||||
still busy). As soon as the transfer of the most recently written byte ends,
|
||||
SIO_STAT.2 becomes set.<br/></p>
|
||||
<h4 id="sio_rx_data-notes">SIO_RX_DATA Notes</h4>
|
||||
<p>The hardware can hold 8 bytes in the RX direction (when receiving further
|
||||
byte(s) while the RX FIFO is full, then the last FIFO entry will by overwritten
|
||||
by the new byte, and SIO_STAT.4 gets set; the hardware does NOT automatically
|
||||
disable RTS when the FIFO becomes full).<br/>
|
||||
Data can be read from SIO_RX_DATA when SIO_STAT.1 is set, that flag gets
|
||||
automatically cleared after reading from SIO_RX_DATA (unless there are still
|
||||
further bytes in the RX FIFO). Note: The hardware does always store incoming
|
||||
data in RX FIFO (even when Parity or Stop bits are invalid).<br/>
|
||||
Note: A 16bit read allows to read two FIFO entries at once; nethertheless, it
|
||||
removes only ONE entry from the FIFO. On the contrary, a 32bit read DOES remove
|
||||
FOUR entries (although, there's nothing that'd indicate if the FIFO did
|
||||
actually contain four entries).<br/>
|
||||
Reading from Empty RX FIFO returns either the most recently received byte or
|
||||
zero (the hardware stores incoming data in ALL unused FIFO entries; eg. if five
|
||||
entries are used, then the data gets stored thrice, after reading 6 bytes, the
|
||||
FIFO empty flag gets set, but nethertheless, the last byte can be read two more
|
||||
times, but doing further reads returns 00h).<br/></p>
|
||||
<h4 id="interrupt-acknowledge-notes">Interrupt Acknowledge Notes</h4>
|
||||
<p>First reset I_STAT.8, then set SIO.CTRL.4 (when doing it vice-versa, the
|
||||
hardware may miss a new IRQ which may occur immediately after setting
|
||||
SIO.CTRL.4) (and I_STAT.8 is edge triggered, so that bit can be reset even
|
||||
while SIO_STAT.9 is still set).<br/>
|
||||
When acknowledging via SIO_CTRL.4 with the enabled condition(s) in
|
||||
SIO_CTRL.10-12 still being true (eg. the RX FIFO is still not empty): the IRQ
|
||||
does trigger again (almost) immediately (it goes off only for a very short
|
||||
moment; barely enough to allow I_STAT.8 to sense a edge).<br/></p>
|
||||
<h4 id="sio_baud-notes">SIO_BAUD Notes</h4>
|
||||
<p>Timer reload occurs when writing to SIO_BAUD, and, automatically when the
|
||||
Baudrate Timer reaches zero. There should be two 16bit SIO timers (for TX and
|
||||
RX), the upper 15bit of one of that timers can be read from SIO_STAT (not sure
|
||||
which one, and no idea if there's a way to read the other timer, too).<br/>
|
||||
Or... maybe there is only ONE timer, and RX/TX are separated only by separate
|
||||
"timer ellapsed" counters, in that case the MUL1 factor won't work properly,
|
||||
but, with the MUL16 or MUL64 factors, RX could start anytime (eg. when TX has
|
||||
already ellapsed a bunch of times)...?<br/>
|
||||
The maximum baud rate may vary depending on the length and quality of the
|
||||
cable, whether and how many inverters and anti-inverters are used (on the
|
||||
mainboard and in external adaptor, and on whether signals are externally
|
||||
converted to +/-12V levels)... anyways, rates up to 9600 baud should be working
|
||||
in all cases.<br/>
|
||||
However, running in no$psx, Wipeout 2097 seems to use about 2 million bauds...
|
||||
although, in older no$psx versions, I believe I did see it using some kind of
|
||||
baudrate detection, where it did try different rates in steps of 200 bauds or
|
||||
so...?<br/></p>
|
||||
<h4 id="sio-ports-vs-joy-ports">SIO Ports vs JOY Ports</h4>
|
||||
<p>SIO uses I/O Addresses 1F801050h..1F80105Fh, which seem to be organized similar
|
||||
to the Controller/Memory Card registers at 1F801040h..1F80104Fh, though not
|
||||
identical, and with an additional register at 1F80105Ch, which has no
|
||||
corresponding port at 1F80104Ch.<br/>
|
||||
SIO_BAUD is \<effectively> same as for JOY_BAUD, but, \<internally>
|
||||
they are a bit different:<br/></p>
|
||||
<pre><code> JOY_BAUD is multiplied by Factor, and does then ellapse "2" times per bit.
|
||||
SIO_BAUD is NOT multiplied, and, instead, ellapses "2*Factor" times per bit.
|
||||
</code></pre>
|
||||
<p>Unlike for the Controller/Memory Card ports, the data is transferred without
|
||||
CLK signal, instead, it's using RS232 format, ie. the transfer starts with a
|
||||
start bit, and is then transferred at a specific baudrate (which must be
|
||||
configured identically at the receiver side). For RS232, data is usually 8bit,
|
||||
and may optionally end with a parity bit, and one or two stop bits.<br/></p>
|
||||
<h4 id="note">Note</h4>
|
||||
<p>For SIO Pinouts, PSone SIO upgrading, and for building RS232 adaptors, see:<br/>
|
||||
<a href="../pinouts/#pinouts-sio-pinouts">Pinouts - SIO Pinouts</a><br/>
|
||||
Aside from the internal SIO port, the PSX BIOS supports two additional external
|
||||
serial ports, connected to the expansion port,<br/>
|
||||
<a href="../expansionportpio/#exp2-dual-serial-port-for-tty-debug-terminal">EXP2 Dual Serial Port (for TTY Debug Terminal)</a><br/></p>
|
||||
<h4 id="sio-games">SIO Games</h4>
|
||||
<p>The SIO ports on two consoles can be connected with an SCPH-1040 Link Cable (known as Taisen Cable, or "Fight Cable" in Japan) for multiplayer functionality on games that support this method. This was used by a small number of games in the console's lifecycle, but inconveniently required a second console and copy of the game.</p>
|
||||
<p>Two-Console Link Cable Games (Incomplete List):</p>
|
||||
<pre><code>Andretti Racing
|
||||
Armored Core (and Armored Core "Link Versus Demo" disc)
|
||||
Armored Core Project Phantasma
|
||||
Armored Core Master of Arena
|
||||
Assault Rigs
|
||||
Ayrton Senna Kart Duel
|
||||
Blast Radius
|
||||
Bogey Dead 6
|
||||
Burning Road
|
||||
Bushido Blade
|
||||
Bushido Blade 2
|
||||
C1 -Circuit-
|
||||
CART World Series
|
||||
Command & Conquer Red Alert
|
||||
Command & Conquer Red Alert Retaliation
|
||||
Cool Boarders 2
|
||||
Dead in the Water
|
||||
Descent
|
||||
Descent Maximum
|
||||
Destruction Derby
|
||||
Duke Nukem Total Meltdown
|
||||
Dodgem Arena
|
||||
Doom
|
||||
Dune 2000
|
||||
Explosive Racing (X Racing in NTSC-J)
|
||||
Final Doom
|
||||
Formula 1
|
||||
Formula 1 98
|
||||
Grand Tour Racing '98 (Gekisou!! Grand Racing -Total Driving'- in NTSC-J, Total Drivin in PAL)
|
||||
Independence Day
|
||||
Krazy Ivan
|
||||
Leading Jockey Highbred
|
||||
Metal Jacket
|
||||
Mobile Suit Z-Gundam
|
||||
Monaco Grand Prix Racing Simulation 2 (Monaco Grand Prix in NTSC-U/C)
|
||||
Motor Toon Grand Prix (reportedly NTSC-U/C version only)
|
||||
Motor Toon Grand Prix 2
|
||||
Motor Toon Grand Prix USA Edition
|
||||
The Need for Speed (Over Drivin' DX in NTSC-J)
|
||||
PrePre Vol. 2
|
||||
Pro Pinball Big Race USA
|
||||
RacinGroovy
|
||||
Real Robots Final Attack
|
||||
Red Asphalt (Rock & Roll Racing 2 Red Asphalt in PAL)
|
||||
Ridge Racer Revolution
|
||||
R4 Ridge Racer Type 4
|
||||
Robo Pit
|
||||
Rogue Trip Vacation 2012
|
||||
San Francisco Rush Extreme Racing (reportedly PAL version only)
|
||||
Shutokou Battle R
|
||||
Sidewinder
|
||||
Sidewinder USA
|
||||
Soukou Kihei Votoms Gaiden: Ao no Kishi Berserga Monogatari
|
||||
Streak Hoverboard Racing
|
||||
Test Drive 4
|
||||
Test Drive Off-Road (reportedly NTSC-U/C only)
|
||||
TOCA 2 Touring Car Challenge (TOCA 2 Touring Cars in PAL)
|
||||
Trick'N Snowboarder (Tricky Sliders Freestyle Snowboard in NTSC-J)
|
||||
Twisted Metal III
|
||||
Wing Over
|
||||
Wipeout
|
||||
Wipeout 3 Special Edition
|
||||
Wipeout XL (Wipeout 2097 in PAL)
|
||||
Zero Pilot Ginyoku no Senshi
|
||||
</code></pre>
|
||||
<p>The serial port is used (for 2-player link) by Wipeout 2097 (that game
|
||||
accidently assumes BAUDs based on 64*1024*1025 Hz rather than on 600h*44100
|
||||
Hz).<br/>
|
||||
Ridge Racer Revolution is also said to support 2P link.<br/>
|
||||
Keitai Eddy seems to allow to connect a mobile phone to the SIO port (the games
|
||||
CD cover suggests so; this seems to be something different than the "normal"
|
||||
I-Mode adaptor, which would connect to controller port, not to SIO port).<br/></p>
|
||||
<h4 id="8251a-note">8251A Note</h4>
|
||||
<p>The Playstation Serial Port is apparently based/inspired on the Intel 8251A
|
||||
USART chip; which has very similar 8bit Mode/Command/Status registers.<br/></p>
|
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|
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1F801108h+N*10h - Timer 0..2 Counter Target Value (R/W)
|
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|
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<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/timers.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="timers">Timers</h1>
|
||||
<h4 id="1f801100hn10h-timer-02-current-counter-value-rw">1F801100h+N*10h - Timer 0..2 Current Counter Value (R/W)</h4>
|
||||
<pre><code> 0-15 Current Counter value (incrementing)
|
||||
16-31 Garbage
|
||||
</code></pre>
|
||||
<p>This register is automatically incrementing. It is write-able (allowing to set
|
||||
it to any value). It gets forcefully reset to 0000h on any write to the Counter
|
||||
Mode register, and on counter overflow (either when exceeding FFFFh, or when
|
||||
exceeding the selected target value).<br/></p>
|
||||
<h4 id="1f801104hn10h-timer-02-counter-mode-rw">1F801104h+N*10h - Timer 0..2 Counter Mode (R/W)</h4>
|
||||
<pre><code> 0 Synchronization Enable (0=Free Run, 1=Synchronize via Bit1-2)
|
||||
1-2 Synchronization Mode (0-3, see lists below)
|
||||
Synchronization Modes for Counter 0:
|
||||
0 = Pause counter during Hblank(s)
|
||||
1 = Reset counter to 0000h at Hblank(s)
|
||||
2 = Reset counter to 0000h at Hblank(s) and pause outside of Hblank
|
||||
3 = Pause until Hblank occurs once, then switch to Free Run
|
||||
Synchronization Modes for Counter 1:
|
||||
Same as above, but using Vblank instead of Hblank
|
||||
Synchronization Modes for Counter 2:
|
||||
0 or 3 = Stop counter at current value (forever, no h/v-blank start)
|
||||
1 or 2 = Free Run (same as when Synchronization Disabled)
|
||||
3 Reset counter to 0000h (0=After Counter=FFFFh, 1=After Counter=Target)
|
||||
4 IRQ when Counter=Target (0=Disable, 1=Enable)
|
||||
5 IRQ when Counter=FFFFh (0=Disable, 1=Enable)
|
||||
6 IRQ Once/Repeat Mode (0=One-shot, 1=Repeatedly)
|
||||
7 IRQ Pulse/Toggle Mode (0=Short Bit10=0 Pulse, 1=Toggle Bit10 on/off)
|
||||
8-9 Clock Source (0-3, see list below)
|
||||
Counter 0: 0 or 2 = System Clock, 1 or 3 = Dotclock
|
||||
Counter 1: 0 or 2 = System Clock, 1 or 3 = Hblank
|
||||
Counter 2: 0 or 1 = System Clock, 2 or 3 = System Clock/8
|
||||
10 Interrupt Request (0=Yes, 1=No) (Set after Writing) (W=1) (R)
|
||||
11 Reached Target Value (0=No, 1=Yes) (Reset after Reading) (R)
|
||||
12 Reached FFFFh Value (0=No, 1=Yes) (Reset after Reading) (R)
|
||||
13-15 Unknown (seems to be always zero)
|
||||
16-31 Garbage (next opcode)
|
||||
</code></pre>
|
||||
<p>In one-shot mode, the IRQ is pulsed/toggled only once (one-shot mode doesn't
|
||||
stop the counter, it just suppresses any further IRQs until a new write to the
|
||||
Mode register occurs; if both IRQ conditions are enabled in Bit4-5, then
|
||||
one-shot mode triggers only one of those conditions; whichever occurs first).<br/>
|
||||
Normally, Pulse mode should be used (Bit10 is permanently set, except for a few
|
||||
clock cycles when an IRQ occurs). In Toggle mode, Bit10 is set after writing to
|
||||
the Mode register, and becomes inverted on each IRQ (in one-shot mode, it
|
||||
remains zero after the IRQ) (in repeat mode it inverts Bit10 on each IRQ, so
|
||||
IRQ4/5/6 are triggered only each 2nd time, ie. when Bit10 changes from 1 to 0).<br/>
|
||||
The "free run" mode is simply saying that the counter will not reset at a given threshold value.</p>
|
||||
<h4 id="1f801108hn10h-timer-02-counter-target-value-rw">1F801108h+N*10h - Timer 0..2 Counter Target Value (R/W)</h4>
|
||||
<pre><code> 0-15 Counter Target value
|
||||
16-31 Garbage
|
||||
</code></pre>
|
||||
<p>When the Target flag is set (Bit3 of the Control register), the counter
|
||||
increments up to (including) the selected target value, and does then restart
|
||||
at 0000h.<br/></p>
|
||||
<h4 id="dotclockhblank">Dotclock/Hblank</h4>
|
||||
<p>For more info on dotclock and hblank timings, see:<br/>
|
||||
<a href="../graphicsprocessingunitgpu/#gpu-timings">GPU Timings</a><br/>
|
||||
Caution: Reading the Current Counter Value can be a little unstable (when using
|
||||
dotclk or hblank as clock source); the GPU clock isn't in sync with the CPU
|
||||
clock, so the timer may get changed during the CPU read cycle. As a workaround:
|
||||
repeat reading the timer until the received value is the same (or slightly
|
||||
bigger) than the previous value.<br/></p>
|
||||
</article>
|
||||
</div>
|
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<a class="md-nav__link" href="../psxdevboardchipsets/">
|
||||
PSX Dev-Board Chipsets
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../hardwarenumbers/">
|
||||
Hardware Numbers
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../pinouts/">
|
||||
Pinouts
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../aboutcredits/">
|
||||
About & Credits
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdromvideocdsvcd/">
|
||||
CDROM Video CDs (VCD)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="../cdrominternalinfoonpsxcdromcontroller/">
|
||||
CDROM Internal Info on PSX CDROM Controller
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-sidebar md-sidebar--secondary" data-md-component="sidebar" data-md-type="toc">
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<div class="md-sidebar__scrollwrap">
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<div class="md-sidebar__inner">
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<nav aria-label="Table of contents" class="md-nav md-nav--secondary">
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<label class="md-nav__title" for="__toc">
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<span class="md-nav__icon md-icon"></span>
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||||
Table of contents
|
||||
</label>
|
||||
<ul class="md-nav__list" data-md-component="toc" data-md-scrollfix="">
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#io-write-datasize">
|
||||
I/O Write Datasize
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#io-read-datasize">
|
||||
I/O Read Datasize
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cache-problems">
|
||||
Cache Problems
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#writebuffer-problems">
|
||||
Writebuffer Problems
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cpu-loadstore-problems">
|
||||
CPU Load/Store Problems
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#cpu-register-problems-r1-at-r26-k0-r29-sp">
|
||||
CPU Register Problems - R1 (AT), R26 (K0), R29 (SP)
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#locked-locations-in-memory-and-io-area">
|
||||
Locked Locations in Memory and I/O Area
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#mirrors-in-io-area">
|
||||
Mirrors in I/O Area
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#garbage-locations-in-io-area">
|
||||
Garbage Locations in I/O Area
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psx-as-abbreviation-for-playstation-1">
|
||||
PSX as Abbreviation for Playstation 1
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psx-as-abbreviation-for-posix1">
|
||||
PSX as Abbreviation for POSIX.1
|
||||
</a>
|
||||
</li>
|
||||
<li class="md-nav__item">
|
||||
<a class="md-nav__link" href="#psx-as-abbreviation-for-an-extended-playstation-2">
|
||||
PSX as Abbreviation for an Extended Playstation 2
|
||||
</a>
|
||||
</li>
|
||||
</ul>
|
||||
</nav>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="md-content" data-md-component="content">
|
||||
<article class="md-content__inner md-typeset">
|
||||
<a class="md-content__button md-icon" href="https://github.com/psx-spx/psx-spx.github.io/edit/master/docs/unpredictablethings.md" title="Edit this page">
|
||||
<svg viewbox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="M20.71 7.04c.39-.39.39-1.04 0-1.41l-2.34-2.34c-.37-.39-1.02-.39-1.41 0l-1.84 1.83 3.75 3.75M3 17.25V21h3.75L17.81 9.93l-3.75-3.75L3 17.25z"></path></svg>
|
||||
</a>
|
||||
<h1 id="unpredictable-things">Unpredictable Things</h1>
|
||||
<p>Normally, I/O ports should be accessed only at their corresponding size (ie.
|
||||
16bit read/write for 16bit ports), and of course, only existing memory and I/O
|
||||
addresses should be used. When not recursing that rules, some more or less
|
||||
(un-)predictable things may happen...<br/></p>
|
||||
<h4 id="io-write-datasize">I/O Write Datasize</h4>
|
||||
<pre><code> Address Content W.8bit W.16bit W.32bit
|
||||
00000000h-00xFFFFFh Main RAM OK OK OK
|
||||
1F800000h-1F8003FFh Scratchpad OK OK OK
|
||||
1F801000h-1F801023h MEMCTRL (w32) (w32) OK
|
||||
1F80104xh JOY_xxx (w16) OK CROP
|
||||
1F80105xh SIO_xxx (w16) OK CROP
|
||||
1F801060h-1F801063h RAM_SIZE (w32) (w32) OK (with crash)
|
||||
1F801070h-1F801077h IRQCTRL (w32) (w32) OK
|
||||
1F8010x0h-1F8010x3h DMAx.ADDR (w32) (w32) OK
|
||||
1F8010x4h-1F8010x7h DMAx.LEN OK OK OK
|
||||
1F8010x8h-1F8010xFh DMAx.CTRL/MIRR (w32) (w32) OK
|
||||
1F8010F0h-1F8010F7h DMA.DPCR/DICR (w32) (w32) OK
|
||||
1F8010F8h-1F8010FFh DMA.unknown IGNORE IGNORE IGNORE
|
||||
1F801100h-1F80110Bh Timer 0 (w32) (w32) OK
|
||||
1F801110h-1F80110Bh Timer 1 (w32) (w32) OK
|
||||
1F801120h-1F80110Bh Timer 2 (w32) (w32) OK
|
||||
1F801800h-1F801803h CDROM OK ? ?
|
||||
1F801810h-1F801813h GPU.GP0 ? ? OK
|
||||
1F801814h-1F801817h GPU.GP1 ? ? OK
|
||||
1F801820h-1F801823h MDEC.CMD/DTA ? ? OK
|
||||
1F801824h-1F801827h MDEC.CTRL ? ? OK
|
||||
1F801C00h-1F801E7Fh SPU (i16) OK OK
|
||||
1F801E80h-1F801FFFh SPU.UNUSED IGNORE IGNORE IGNORE
|
||||
1F802020h-1F80202Fh DUART OK ? ?
|
||||
1F802041h POST OK ? ?
|
||||
FFFE0130h-FFFE0133h CACHE.CTRL (i32) (i32) OK
|
||||
</code></pre>
|
||||
<p>Whereas,<br/></p>
|
||||
<pre><code> OK works
|
||||
(w32) write full 32bits (left-shifted if address isn't word-aligned)
|
||||
(w16) write full 16bits (left-shifted if address isn't halfword-aligned)
|
||||
(i32) write full 32bits (ignored if address isn't word-aligned)
|
||||
(i16) write full 16bits (ignored if address isn't halfword-aligned)
|
||||
CROP write only lower 16bit (and leave upper 16bit unchanged)
|
||||
</code></pre>
|
||||
<p>It's somewhat "legit" to use 16bit writes on 16bit registers like RAM_SIZE,
|
||||
I_STAT, I_MASK, and Timer 0-2.<br/>
|
||||
Non-4-byte aligned 8bit/16bit writes to RAM_SIZE do crash (probably because the
|
||||
"(w32)" effect is left-shifting the value, so lower 8bit become zero).<br/>
|
||||
Results on unaligned I/O port writes (via SWL/SWR opcodes) are unknown.<br/></p>
|
||||
<h4 id="io-read-datasize">I/O Read Datasize</h4>
|
||||
<p>In most cases, I/O ports can be read in 8bit, 16bit, or 32bit units, regardless
|
||||
of their size, among others allowing to read two 16bit ports at once with a
|
||||
single 32bit read. If there's only one 16bit port within a 32bit region, then
|
||||
32bit reads often return garbage in the unused 16bits. Also, 8bit or 16bit VRAM
|
||||
data reads via GPUREAD probably won't work? Expansion 2 Region can be accessed
|
||||
only via 8bit reads, and 16bit/32bit reads seem to cause exceptions (or rather:
|
||||
no such exception!) (except, probably 16bit reads are allowed when the region
|
||||
is configured to 16bit databus width).<br/>
|
||||
There are at least some special cases:<br/></p>
|
||||
<pre><code> FFFE0130h-FFFE0133h 8bit (+16bit?) read works ONLY from word-aligned address
|
||||
</code></pre>
|
||||
<h4 id="cache-problems">Cache Problems</h4>
|
||||
<p>The functionality of the Cache is still widely unknown. Not sure if DMA
|
||||
transfers are updating or invalidating cache. Cached Data within KSEG0 should
|
||||
be automatically also cached at the corresponding mirrored address in KUSEG and
|
||||
vice versa. Mirrors within KSEG1 (or within KUSEG) may be a different thing,
|
||||
eg. when using addresses spead across the first 8MB region to access the 2MB
|
||||
RAM. Same problems may occor for Expansion and BIOS mirrors, although, not sure
|
||||
if that regions are cached.<br/></p>
|
||||
<h4 id="writebuffer-problems">Writebuffer Problems</h4>
|
||||
<p>The writebuffer seems to be disabled for the normal I/O area at 1F801000h,
|
||||
however, it appears to be enabled for the Expansion I/O region at 1F802000h
|
||||
(after writing to 1F802041h, the BIOS issues 4 dummy writes to RAM, apparently
|
||||
(?) in order to flush the writebuffer). The same might apply for Expansion
|
||||
Memory region at 1F000000h, although usually that region would contain ROM, so
|
||||
it'd be don't care whether it is write-buffered or not.<br/></p>
|
||||
<h4 id="cpu-loadstore-problems">CPU Load/Store Problems</h4>
|
||||
<p>XXcpuREG ---> applies ONLY to LOAD (not to store)<br/>
|
||||
Memory read/write opcodes take a 1-cycle delay until the data arrives at the
|
||||
destination, ie. the next opcode should not use the destination register (or
|
||||
more unlikely, the destination memory location) as source operand. Usually,
|
||||
when trying to do so, the second opcode would receive the OLD value - however,
|
||||
if an exception occurs between the two opcodes, then the read/write operation
|
||||
may finish, and the second opcode would probably receive the NEW value.<br/></p>
|
||||
<h4 id="cpu-register-problems-r1-at-r26-k0-r29-sp">CPU Register Problems - R1 (AT), R26 (K0), R29 (SP)</h4>
|
||||
<p>Exception handlers cannot preserve all registers, before returning, they must
|
||||
load the return address into a general purpose register (conventionally R26 aka
|
||||
K0), so be careful not to use that register, unless you are 100% sure that no
|
||||
interrupts and no other exceptions can occur. Some exception handlers might
|
||||
also destroy R27 aka K1 (though execption handler in the PSX Kernel leaves that
|
||||
register unchanged).<br/>
|
||||
Some assemblers (not a22i in nocash syntax mode) are internally using R1 aka AT
|
||||
as scratch register for some pseudo opcodes, including for a "sw rx,imm32"
|
||||
pseudo opcode (which is nearly impossible to separate from the normal "sw
|
||||
rx,imm16" opcode), be careful not to use R1, unless you can trust your
|
||||
assembler not to destroy that register behind your back.<br/>
|
||||
The PSX Kernel uses "Full-Decrementing-Wasted-Stack", where "Wasted" means that
|
||||
when calling a sub-function with N parameters, then the caller must
|
||||
pre-allocate N works on stack, and the sub-function may freely use and destroy
|
||||
these words; at [SP+0..N*4-1].<br/></p>
|
||||
<h4 id="locked-locations-in-memory-and-io-area">Locked Locations in Memory and I/O Area</h4>
|
||||
<pre><code> 00800000h ;-when Main RAM configured to end at 7FFFFFh
|
||||
1F080000h 780000h ;-when Expansion 1 configured to end at 7FFFFh
|
||||
1F800400h C00h ;-region after Scratchpad
|
||||
1F801024h 1Ch ;\
|
||||
1F801064h 0Ch ;
|
||||
1F801078h 08h ;
|
||||
1F801140h 6C0h ; gaps in I/O region
|
||||
1F801804h 0Ch ;
|
||||
1F801818h 08h ;
|
||||
1F801828h 3D8h ;/
|
||||
1F802080h 3FDF80h ;-when Expansion 2 configured to end at 7Fh
|
||||
1FC80000h 60380000h ;-when BIOS ROM configured to end at 7FFFFh
|
||||
C0000000h 1FFE0000h ;\
|
||||
FFFE0020h E0h ; gaps in KSEG2 (cache control region)
|
||||
FFFE0140h 1FEC0h ;/
|
||||
</code></pre>
|
||||
<p>Trying to access these locations generates an exception. For KSEG0 and KSEG1,
|
||||
locked regions are same as for first 512MB of KUSEG.<br/></p>
|
||||
<h4 id="mirrors-in-io-area">Mirrors in I/O Area</h4>
|
||||
<pre><code> 1F80108Ch+N*10h - D#_CHCR Mirrors - (N=0..6, for DMA channel 0..6)
|
||||
</code></pre>
|
||||
<p>Read/writeable mirrors of DMA Control registers at 1F801088h+N*10h.<br/></p>
|
||||
<h4 id="garbage-locations-in-io-area">Garbage Locations in I/O Area</h4>
|
||||
<pre><code> 1F801062h (2 bytes) ;\
|
||||
1F801072h (2 bytes) ; unused addresses in Memory and Interrupt Control area
|
||||
1F801076h (2 bytes) ;/
|
||||
1F801102h (2 bytes) ;\
|
||||
1F801106h (2 bytes) ; unused addresses in Timer 0 area
|
||||
1F80110Ah (6 bytes) ;/
|
||||
1F801112h (2 bytes) ;\
|
||||
1F801116h (2 bytes) ; unused addresses in Timer 1 area
|
||||
1F80111Ah (6 bytes) ;/
|
||||
1F801122h (2 bytes) ;\
|
||||
1F801126h (2 bytes) ; unused addresses in Timer 2 area and next some bytes
|
||||
1F80112Ah (22 bytes) ;/
|
||||
1F801820h (4 bytes) ;-read MDEC Data-Out port (if there is no data)
|
||||
FFFE0000h (32 bytes) ;\
|
||||
FFFE0100h (48 bytes) ; unused addresses in Cache control area
|
||||
FFFE0132h (2 bytes) ; (including write-only upper 16bit of Port FFFE0130h)
|
||||
FFFE0134h (12 bytes) ;/
|
||||
</code></pre>
|
||||
<p>Unlike all other unused I/O addresses, these addresses are unlocked (ie. they
|
||||
do not trigger exceptions on access), however they do not seem to contain
|
||||
anything useful. The BIOS never seems to use them. Writing any values to them
|
||||
seems to have no effect. And reading acts somewhat unstable:<br/>
|
||||
Usually returns zeros in most cases. Except that, the first byte on a 10h-byte
|
||||
boundary often returns the lower 8bit of the memory address (eg.
|
||||
[FFFE0010h]=10h). And, when [FFFE0130h].Bit11=0, then reading from these
|
||||
registers does return the 32bit opcode that is to be executed next (or at some
|
||||
locations, the opcode thereafter).<br/></p>
|
||||
<h4 id="psx-as-abbreviation-for-playstation-1">PSX as Abbreviation for Playstation 1</h4>
|
||||
<p>In gaming and programming scene, "PSX" is most commonly used as abbreviation
|
||||
for the original Playstation series (occasionally including PSone). Sony has
|
||||
never officially used that abbreviation, however, the Playstation BIOS contains
|
||||
the ASCII strings "PSX" and "PS-X" here and there. The letters "PS" are widely
|
||||
believed to stand for PlayStation, and the meaning of the "X" is totally
|
||||
unknown (although, actually it may stand for POSIX.1, see below).<br/></p>
|
||||
<h4 id="psx-as-abbreviation-for-posix1">PSX as Abbreviation for POSIX.1</h4>
|
||||
<p>According to JMI Software Systems, "PSX" is a trademark of themselves, and
|
||||
stands for "single-user, single-group, subset of POSIX.1" (POSIX stands for
|
||||
something commonly used by HLL programmers under UNIX or so). That "PSX" kernel
|
||||
from JMI is available for various processors, including MIPS processors, and
|
||||
like the playstation, it does include functions like "atoi", and does support
|
||||
TTY access via Signetics 2681 DUART chips. The DTL-H2000 does also have
|
||||
POSIX-style "PSX>" prompt. So, altogether, it's quite possible that Sony has
|
||||
licensed the kernel from JMI.<br/></p>
|
||||
<h4 id="psx-as-abbreviation-for-an-extended-playstation-2">PSX as Abbreviation for an Extended Playstation 2</h4>
|
||||
<p>As everybody agrees, PSX should be used only as abbreviation for Playstation 1,
|
||||
and nobody should never ever use it for the Playstation 2. Well, nobody, except
|
||||
Sony... despite of the common use as abbreviation for Playstation 1 (and
|
||||
despite of the JMI trademark)... in 2003, Sony has have released a "Playstation
|
||||
2 with built-in HDD/DVD Videorecorder" and called that thing "PSX" for the best
|
||||
of confusion.<br/></p>
|
||||
</article>
|
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|
||||
<script src="../assets/javascripts/bundle.4ea5477f.min.js"></script>
|
||||
</body>
|
||||
</html>
|
||||
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Reference in New Issue