193 lines
9.5 KiB
Markdown
193 lines
9.5 KiB
Markdown
# DMA Channels
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#### DMA Register Summary
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```
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1F80108xh DMA0 channel 0 MDECin (RAM to MDEC)
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1F80109xh DMA1 channel 1 MDECout (MDEC to RAM)
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1F8010Axh DMA2 channel 2 GPU (lists + image data)
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1F8010Bxh DMA3 channel 3 CDROM (CDROM to RAM)
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1F8010Cxh DMA4 channel 4 SPU
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1F8010Dxh DMA5 channel 5 PIO (Expansion Port)
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1F8010Exh DMA6 channel 6 OTC (reverse clear OT) (GPU related)
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1F8010F0h DPCR - DMA Control register
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1F8010F4h DICR - DMA Interrupt register
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```
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These ports control DMA at the CPU-side. In most cases, you'll additionally
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need to initialize an address (and transfer direction, transfer enabled, etc.)
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at the remote-side (eg. at the GPU-side for DMA2).<br/>
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#### 1F801080h+N\*10h - D#\_MADR - DMA base address (Channel 0..6) (R/W)
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```
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0-23 Memory Address where the DMA will start reading from/writing to
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24-31 Not used (always zero)
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```
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In SyncMode=0, the hardware doesn't update the MADR registers (it will contain
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the start address even during and after the transfer) (unless Chopping is
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enabled, in that case it does update MADR, same does probably also happen when
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getting interrupted by a higher priority DMA channel).<br/>
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In SyncMode=1 and SyncMode=2, the hardware does update MADR (it will contain
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the start address of the currently transferred block; at transfer end, it'll
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hold the end-address in SyncMode=1, or the 00FFFFFFh end-code in SyncMode=2)<br/>
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Note: Address bit0-1 are writeable, but any updated current/end addresses are
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word-aligned with bit0-1 forced to zero.<br/>
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#### 1F801084h+N\*10h - D#\_BCR - DMA Block Control (Channel 0..6) (R/W)
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For SyncMode=0 (ie. for OTC and CDROM):<br/>
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```
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0-15 BC Number of words (0001h..FFFFh) (or 0=10000h words)
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16-31 0 Not used (usually 0 for OTC, or 1 ("one block") for CDROM)
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```
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For SyncMode=1 (ie. for MDEC, SPU, and GPU-vram-data):<br/>
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```
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0-15 BS Blocksize (words) ;for GPU/SPU max 10h, for MDEC max 20h
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16-31 BA Amount of blocks ;ie. total length = BS*BA words
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```
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For SyncMode=2 (ie. for GPU-command-lists):<br/>
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```
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0-31 0 Not used (should be zero) (transfer ends at END-CODE in list)
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```
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BC/BS/BA can be in range 0001h..FFFFh (or 0=10000h). For BS, take care not to
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set the blocksize larger than the buffer of the corresponding unit can hold.
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(GPU and SPU both have a 16-word buffer). A larger blocksize means faster
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transfer.<br/>
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SyncMode=1 decrements BA to zero, SyncMode=0 with chopping enabled decrements
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BC to zero (aside from that two cases, D#\_BCR isn't changed during/after
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transfer).<br/>
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#### 1F801088h+N\*10h - D#\_CHCR - DMA Channel Control (Channel 0..6) (R/W)
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```
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0 Transfer Direction (0=To Main RAM, 1=From Main RAM)
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1 Memory Address Step (0=Forward;+4, 1=Backward;-4)
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2-7 Not used (always zero)
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8 Chopping Enable (0=Normal, 1=Chopping; run CPU during DMA gaps)
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9-10 SyncMode, Transfer Synchronisation/Mode (0-3):
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0 Start immediately and transfer all at once (used for CDROM, OTC)
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1 Sync blocks to DMA requests (used for MDEC, SPU, and GPU-data)
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2 Linked-List mode (used for GPU-command-lists)
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3 Reserved (not used)
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11-15 Not used (always zero)
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16-18 Chopping DMA Window Size (1 SHL N words)
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19 Not used (always zero)
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20-22 Chopping CPU Window Size (1 SHL N clks)
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23 Not used (always zero)
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24 Start/Busy (0=Stopped/Completed, 1=Start/Enable/Busy)
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25-27 Not used (always zero)
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28 Start/Trigger (0=Normal, 1=Manual Start; use for SyncMode=0)
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29 Unknown (R/W) Pause? (0=No, 1=Pause?) (For SyncMode=0 only?)
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30 Unknown (R/W)
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31 Not used (always zero)
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```
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The Start/Trigger bit is automatically cleared upon BEGIN of the transfer, this
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bit needs to be set only in SyncMode=0 (setting it in other SyncModes would
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force the first block to be transferred instantly without DRQ, which isn't
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desired).<br/>
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The Start/Busy bit is automatically cleared upon COMPLETION of the transfer,
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this bit must be always set for all SyncModes when starting a transfer.<br/>
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For DMA6/OTC there are some restrictions, D6\_CHCR has only three
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read/write-able bits: Bit24,28,30. All other bits are read-only: Bit1 is always
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1 (step=backward), and the other bits are always 0.<br/>
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#### 1F8010F0h - DPCR - DMA Control Register (R/W)
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```
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0-2 DMA0, MDECin Priority (0..7; 0=Highest, 7=Lowest)
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3 DMA0, MDECin Master Enable (0=Disable, 1=Enable)
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4-6 DMA1, MDECout Priority (0..7; 0=Highest, 7=Lowest)
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7 DMA1, MDECout Master Enable (0=Disable, 1=Enable)
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8-10 DMA2, GPU Priority (0..7; 0=Highest, 7=Lowest)
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11 DMA2, GPU Master Enable (0=Disable, 1=Enable)
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12-14 DMA3, CDROM Priority (0..7; 0=Highest, 7=Lowest)
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15 DMA3, CDROM Master Enable (0=Disable, 1=Enable)
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16-18 DMA4, SPU Priority (0..7; 0=Highest, 7=Lowest)
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19 DMA4, SPU Master Enable (0=Disable, 1=Enable)
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20-22 DMA5, PIO Priority (0..7; 0=Highest, 7=Lowest)
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23 DMA5, PIO Master Enable (0=Disable, 1=Enable)
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24-26 DMA6, OTC Priority (0..7; 0=Highest, 7=Lowest)
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27 DMA6, OTC Master Enable (0=Disable, 1=Enable)
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28-30 Unknown, Priority Offset or so? (R/W)
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31 Unknown, no effect? (R/W)
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```
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Initial value on reset is 07654321h. If two or more channels have the same
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priority setting, then the priority is determined by the channel number
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(DMA0=Lowest, DMA6=Highest).<br/>
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#### 1F8010F4h - DICR - DMA Interrupt Register (R/W)
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```
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0-5 Unknown (read/write-able)
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6-14 Not used (always zero)
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15 Force IRQ (sets bit31) (0=None, 1=Force Bit31=1)
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16-22 IRQ Enable for DMA0..DMA6 (0=None, 1=Enable)
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23 IRQ Master Enable for DMA0..DMA6 (0=None, 1=Enable)
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24-30 IRQ Flags for DMA0..DMA6 (0=None, 1=IRQ) (Write 1 to reset)
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31 IRQ Master Flag (0=None, 1=IRQ) (Read only)
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```
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IRQ flags in Bit(24+n) are set upon DMAn completion - but caution - they are
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set ONLY if enabled in Bit(16+n).<br/>
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Bit31 is a simple readonly flag that follows the following rules:<br/>
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```
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IF b15=1 OR (b23=1 AND (b16-22 AND b24-30)>0) THEN b31=1 ELSE b31=0
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```
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Upon 0-to-1 transition of Bit31, the IRQ3 flag (in Port 1F801070h) gets set.<br/>
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Bit24-30 are acknowledged (reset to zero) when writing a "1" to that bits (and,
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additionally, IRQ3 must be acknowledged via Port 1F801070h).<br/>
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#### 1F8010F8h (usually 7FFAC68Bh? or 0BFAC688h)
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```
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(changes to 7FE358D1h after DMA transfer)
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```
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#### 1F8010FCh (usually 00FFFFF7h) (...maybe OTC fill-value)
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```
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(stays so even after DMA transfer)
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```
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Contains strange read-only values (but not the usual "Garbage").<br/>
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Not yet tested during transfer, might be remaining length and address?<br/>
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#### Commonly used DMA Control Register values for starting DMA transfers
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```
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DMA0 MDEC.IN 01000201h (always)
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DMA1 MDEC.OUT 01000200h (always)
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DMA2 GPU 01000200h (VramRead), 01000201h (VramWrite), 01000401h (List)
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DMA3 CDROM 11000000h (normal), 11400100h (chopped, rarely used)
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DMA4 SPU 01000201h (write), 01000200h (read, rarely used)
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DMA5 PIO N/A (not used by any known games)
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DMA6 OTC 11000002h (always)
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```
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XXX: DMA2 values 01000201h (VramWrite), 01000401h (List) aren't 100% confirmed
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to be used by ALL existing games. All other values are always used as listed
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above.<br/>
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#### DMA Transfer Rates
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```
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DMA0 MDEC.IN 1 clk/word ;0110h clks per 100h words ;\plus whatever
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DMA1 MDEC.OUT 1 clk/word ;0110h clks per 100h words ;/decompression time
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DMA2 GPU 1 clk/word ;0110h clks per 100h words ;-plus ...
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DMA3 CDROM/BIOS 24 clks/word ;1800h clks per 100h words ;\plus single/double
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DMA3 CDROM/GAMES 40 clks/word ;2800h clks per 100h words ;/speed sector rate
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DMA4 SPU 4 clks/word ;0420h clks per 100h words ;-plus ...
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DMA5 PIO 20 clks/word ;1400h clks per 100h words ;-not actually used
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DMA6 OTC 1 clk/word ;0110h clks per 100h words ;-plus nothing
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```
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MDEC decompression time is still unknown (may vary on RLE and color/mono).<br/>
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GPU polygon rendering time is unknown (may be quite slow for large polys).<br/>
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GPU vram read/write time is unknown (may vary on horizontal screen resolution).<br/>
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CDROM BIOS default is 24 clks, for some reason most games change it to 40 clks.<br/>
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SPU transfer is unknown (may have some extra delays).<br/>
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XXX is SPU really only 4 clks (theoretically SPU access should be slower)?<br/>
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PIO isn't used by any games (and if used: could be configured to other rates)<br/>
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OTC is just writing to RAM without extra overload.<br/>
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CDROM/SPU/PIO timings can be configured via Memory Control registers.<br/>
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#### DRAM Hyper Page mode
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DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock
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cycle per word (effectively around 17 clks per 16 words, due to required row
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address loading, probably plus some further minimal overload due to refresh
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cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM
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access takes 1 opcode cycle plus 6 waitstates, ie. 7 cycles in total)<br/>
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#### CPU Operation during DMA
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Basically, the CPU is stopped during DMA (theoretically, the CPU could be kept
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running when accessing only cache, scratchpad and on-chip I/O ports like DMA
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registers, and during the CDROM/SPU/PIO waitstates it could even access Main
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RAM, but these situations aren't supported).<br/>
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However, the CPU operation resumes during periods when DMA gets interrupted
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(ie. after SyncMode 1 blocks, after SyncMode 2 list entries) (or in SyncMode 0
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with Chopping enabled).<br/>
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