74 lines
3.6 KiB
Markdown
74 lines
3.6 KiB
Markdown
# Interrupts
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#### 1F801070h I\_STAT - Interrupt status register (R=Status, W=Acknowledge)
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#### 1F801074h I\_MASK - Interrupt mask register (R/W)
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Status: Read I\_STAT (0=No IRQ, 1=IRQ)<br/>
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Acknowledge: Write I\_STAT (0=Clear Bit, 1=No change)<br/>
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Mask: Read/Write I\_MASK (0=Disabled, 1=Enabled)<br/>
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```
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0 IRQ0 VBLANK (PAL=50Hz, NTSC=60Hz)
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1 IRQ1 GPU Can be requested via GP0(1Fh) command (rarely used)
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2 IRQ2 CDROM
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3 IRQ3 DMA
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4 IRQ4 TMR0 Timer 0 aka Root Counter 0 (Sysclk or Dotclk)
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5 IRQ5 TMR1 Timer 1 aka Root Counter 1 (Sysclk or H-blank)
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6 IRQ6 TMR2 Timer 2 aka Root Counter 2 (Sysclk or Sysclk/8)
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7 IRQ7 Controller and Memory Card - Byte Received Interrupt
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8 IRQ8 SIO
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9 IRQ9 SPU
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10 IRQ10 Controller - Lightpen Interrupt (reportedly also PIO...?)
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11-15 Not used (always zero)
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16-31 Garbage
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```
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#### Secondary IRQ10 Controller (Port 1F802030h)
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[EXP2 DTL-H2000 I/O Ports](expansionportpio.md#exp2-dtl-h2000-io-ports)<br/>
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#### Interrupt Request / Execution
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The interrupt request bits in I\_STAT are edge-triggered, ie. the get set ONLY
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if the corresponding interrupt source changes from "false to true".<br/>
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If one or more interrupts are requested and enabled, ie. if "(I\_STAT AND
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I\_MASK)=nonzero", then cop0r13.bit10 gets set, and when cop0r12.bit10 and
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cop0r12.bit0 are set, too, then the interrupt gets executed.<br/>
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#### Interrupt Acknowledge
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To acknowledge an interrupt, write a "0" to the corresponding bit in I\_STAT.
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Most interrupts (except IRQ0,4,5,6) must be additionally acknowledged at the
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I/O port that has caused them (eg. JOY\_CTRL.bit4).<br/>
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Observe that the I\_STAT bits are edge-triggered (they get set only on
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High-to-Low, or False-to-True edges). The correct acknowledge order is:<br/>
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```
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First, acknowledge I_STAT (eg. I_STAT.bit7=0)
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Then, acknowledge corresponding I/O port (eg. JOY_CTRL.bit4=1)
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```
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When doing it vice-versa, the hardware may miss further IRQs (eg. when first
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setting JOY\_CTRL.4=1, then a new IRQ may occur in JOY\_STAT.4 within a single
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clock cycle, thereafter, setting I\_STAT.7=0 would successfully reset I\_STAT.7,
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but, since JOY\_STAT.4 is already set, there'll be no further edge, so I\_STAT.7
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won't be ever set in future).<br/>
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#### COP0 Interrupt Handling
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Relevant COP0 registers are cop0r13 (CAUSE, reason flags), and cop0r12 (SR,
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control flags), and cop0r14 (EPC, return address), and, cop0cmd=10h (aka RFE
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opcode) is used to prepare the return from interrupts. For more info, see<br/>
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[COP0 - Exception Handling](cpuspecifications.md#cop0---exception-handling)<br/>
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#### PSX specific COP0 Notes
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COP0 has six hardware interrupt bits, of which, the PSX uses only cop0r13.bit10
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(the other ones, cop0r13.bit11-15 are always zero). cop0r13.bit10 is NOT a
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latch, ie. it gets automatically cleared as soon as "(I\_STAT AND I\_MASK)=zero",
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so there's no need to do an acknowledge at the cop0 side. COP0 additionally has
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two software interrupt bits, cop0r13.bit8-9, which do exist in the PSX, too,
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these bits are read/write-able latches which can be set/cleared manually to
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request/acknowledge exceptions by software.<br/>
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#### Halt Function (Wait for Interrupt)
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The PSX doesn't have a HALT opcode, so, even if the program is merely waiting
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for an interrupt to occur, the CPU is always running at full speed, which is
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resulting in high power consumption, and, in case of emulators, high CPU
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emulation load. To save energy, and to make emulation smoother on slower
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computers, I've added a Halt function for use in emulators:<br/>
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[EXP2 Nocash Emulation Expansion](expansionportpio.md#exp2-nocash-emulation-expansion)<br/>
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