1
0
mirror of https://gitlab.os-k.eu/os-k-team/kvisc.git synced 2023-08-25 14:05:46 +02:00
kvisc/vm/pc/regs.c

190 lines
4.0 KiB
C
Raw Normal View History

2019-05-15 20:06:45 +02:00
// The OS/K Team licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
2019-05-15 19:26:40 +02:00
2019-06-21 22:19:55 +02:00
#include <pc/device.h>
2019-05-15 19:26:40 +02:00
2019-06-16 12:48:30 +02:00
reg_t arch_r[] =
2019-05-15 19:26:40 +02:00
{
2019-06-18 12:58:26 +02:00
{ "inv", RES },
2019-07-01 21:46:36 +02:00
{ "flg", GPR },
2019-07-01 00:45:08 +02:00
{ "rip", GPR },
{ "rpc", GPR },
2019-07-01 21:46:36 +02:00
{ "px0", RES },
{ "px1", RES },
2019-07-01 00:45:08 +02:00
{ "fc1", RES },
{ "fc2", RES },
{ "sa0", SYS },
{ "sa1", SYS },
{ "sa2", SYS },
{ "sa3", SYS },
{ "sa4", SYS },
{ "sa5", SYS },
{ "sa6", SYS },
{ "sa7", SYS },
{ "dr0", SYS },
{ "dr1", SYS },
{ "dr2", SYS },
{ "dr3", SYS },
{ "dr4", SYS },
{ "dr5", SYS },
{ "dr6", SYS },
{ "dr7", SYS },
{ "cr0", CTL },
{ "cr1", CTL },
{ "cr2", CTL },
{ "cr3", CTL },
{ "cr4", CTL },
{ "cr5", CTL },
{ "cr6", CTL },
{ "cr7", CTL },
2019-06-18 12:58:26 +02:00
{ "rax", GPR },
{ "rbx", GPR },
{ "rcx", GPR },
{ "rdx", GPR },
{ "rsi", GPR },
{ "rdi", GPR },
2019-07-01 00:45:08 +02:00
{ "rbp", GPR },
{ "rsp", GPR },
{ "rx8", GPR },
{ "rx9", GPR },
{ "r10", GPR },
{ "r11", GPR },
{ "r12", GPR },
{ "r13", GPR },
{ "r14", GPR },
{ "r15", GPR },
{ "r16", GPR },
{ "r17", GPR },
{ "r18", GPR },
{ "r19", GPR },
{ "r20", GPR },
{ "r21", GPR },
{ "r22", GPR },
{ "r23", GPR },
{ "r24", GPR },
{ "r25", GPR },
{ "r26", GPR },
{ "r27", GPR },
{ "r28", GPR },
{ "r29", GPR },
{ "r30", GPR },
{ "r31", GPR },
2019-06-18 12:58:26 +02:00
{ "ax0", GPR },
{ "ax1", GPR },
{ "ax2", GPR },
{ "ax3", GPR },
{ "ax4", GPR },
{ "ax5", GPR },
{ "ax6", GPR },
{ "ax7", GPR },
2019-07-01 00:45:08 +02:00
{ "ax8", GPR },
{ "ax9", GPR },
{ "a10", GPR },
{ "a11", GPR },
{ "a12", GPR },
{ "a13", GPR },
{ "a14", GPR },
{ "a15", GPR },
{ "a16", GPR },
{ "a17", GPR },
{ "a18", GPR },
{ "a19", GPR },
{ "a20", GPR },
{ "a21", GPR },
{ "a22", GPR },
{ "a23", GPR },
{ "a24", GPR },
{ "a25", GPR },
{ "a26", GPR },
{ "a27", GPR },
{ "a28", GPR },
{ "a29", GPR },
{ "a30", GPR },
{ "a31", GPR },
2019-06-18 12:58:26 +02:00
2019-07-01 00:45:08 +02:00
{ "nx0", GPR },
{ "nx1", GPR },
{ "nx2", GPR },
{ "nx3", GPR },
{ "nx4", GPR },
{ "nx5", GPR },
{ "nx6", GPR },
{ "nx7", GPR },
{ "nx8", GPR },
{ "nx9", GPR },
{ "n10", GPR },
{ "n11", GPR },
{ "n12", GPR },
{ "n13", GPR },
{ "n14", GPR },
{ "n15", GPR },
{ "n16", GPR },
{ "n17", GPR },
{ "n18", GPR },
{ "n19", GPR },
{ "n20", GPR },
{ "n21", GPR },
{ "n22", GPR },
{ "n23", GPR },
{ "n24", GPR },
{ "n25", GPR },
{ "n26", GPR },
{ "n27", GPR },
{ "n28", GPR },
{ "n29", GPR },
{ "n30", GPR },
{ "n31", GPR },
2019-05-15 19:26:40 +02:00
};
2019-07-01 00:45:08 +02:00
static_assert(NREGS <= 256, "");
static_assert(sizeof(arch_r)/sizeof(reg_t) == NREGS, "");
2019-06-14 13:34:24 +02:00
#define DUMPREGS(down, up) \
for (i = down; i <= up; i++) { \
if (i % 4 == 0) \
2019-06-19 21:41:22 +02:00
trace("\n"); \
2019-06-14 13:34:24 +02:00
r = &ctx->r[i]; \
2019-06-19 21:41:22 +02:00
trace("%s=0x%-16lX ", r->name, R(i)); \
2019-06-14 13:34:24 +02:00
} \
2019-05-29 16:57:22 +02:00
void dumpregs(ctx_t *ctx)
{
int i;
reg_t *r;
2019-05-30 12:44:56 +02:00
2019-06-21 22:19:55 +02:00
trace("Current RFRAME index: #%lu\n", rfs_current_idx);
2019-06-14 13:34:24 +02:00
2019-07-01 00:45:08 +02:00
DUMPREGS(RAX, R15);
trace("\n");
DUMPREGS(AX0, A15);
2019-06-23 21:12:25 +02:00
trace("\n");
2019-07-01 00:45:08 +02:00
DUMPREGS(NX0, N15);
2019-06-14 13:34:24 +02:00
2019-06-19 21:41:22 +02:00
trace("\n");
2019-06-23 21:12:25 +02:00
DUMPREGS(SA0, SA7);
DUMPREGS(CR0, CR7);
2019-06-14 13:34:24 +02:00
2019-06-25 21:51:53 +02:00
trace("\n\nrip=0x%-16lX rpc=0x%-16lX rsp=0x%-16lX rbp=0x%-16lX",
rip, rpc, rsp, rbp);
2019-06-14 16:47:01 +02:00
2019-07-01 00:45:08 +02:00
trace("\nfc0=0d%-16lu fc1=0d%-16lu fc2=0d%-16lu flg=0x%-16lX",
2019-06-23 21:12:25 +02:00
rx0, rx1, rx2, flg);
2019-06-14 13:34:24 +02:00
2019-06-23 21:12:25 +02:00
trace("\n\nCF=%x OF=%x\n"
2019-06-19 21:41:22 +02:00
"ZF=%x SF=%x\n"
"PF=%x DF=%x\n"
"IF=%x UF=%x\n",
!!(flg&CF), !!(flg&OF),
!!(flg&ZF), !!(flg&SF),
!!(flg&PF), !!(flg&DF),
!!(cr0&IF), !!(cr0&UF));
2019-06-18 22:56:41 +02:00
assert(inv == 0);
2019-05-29 16:57:22 +02:00
}